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公开(公告)号：US20120182797A1
公开(公告)日：2012-07-19
申请号：US13009540
申请日：2011-01-19
申请人： Yijie Zhao , Akira Goda , Mark A. Helm
发明人： Yijie Zhao , Akira Goda , Mark A. Helm
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C16/3422 , G11C2211/5641
摘要： Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.
摘要翻译： 公开了用于感测和存储器件的方法。 一种用于感测的方法确定与要感测的m位存储器单元相邻的n位存储器单元的阈值电压。 要感测的m位存储器单元的控制栅极利用响应于所确定的n位存储单元的阈值电压而调整的感测电压进行偏置。
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公开(公告)号：US08374028B2
公开(公告)日：2013-02-12
申请号：US13009540
申请日：2011-01-19
申请人： Yijie Zhao , Akira Goda , Mark A. Helm
发明人： Yijie Zhao , Akira Goda , Mark A. Helm
IPC分类号： G11C16/00
CPC分类号： G11C16/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C16/3422 , G11C2211/5641
摘要： Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.
摘要翻译： 公开了用于感测和存储器件的方法。 一种用于感测的方法确定与要感测的m位存储器单元相邻的n位存储器单元的阈值电压。 要感测的m位存储器单元的控制栅极利用响应于所确定的n位存储单元的阈值电压而调整的感测电压进行偏置。
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公开(公告)号：US08144516B2
公开(公告)日：2012-03-27
申请号：US12630332
申请日：2009-12-03
申请人： Yijie Zhao , Akira Goda , Jian Li , Haitao Liu
发明人： Yijie Zhao , Akira Goda , Jian Li , Haitao Liu
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/26 , G11C16/3418
摘要： Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass voltage is reduced on the adjacent memory cell. The adjacent memory cell can be on the drain side, the source side, or both drain and source sides of the selected memory cell.
摘要翻译： 公开了用于感测和存储器件的方法。 用于感测的一种这样的方法在与选定的存储器单元相邻的至少一个相邻存储器单元上使用动态通过电压用于编程。 如果相邻存储单元未编程，则相邻存储单元上的通过电压降低。 相邻的存储单元可以在所选存储单元的漏极侧，源极侧或漏极和源极侧。
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4.发明申请APPARATUSES AND METHODS COMPRISING A CHANNEL REGION HAVING DIFFERENT MINORITY CARRIER LIFETIMES 有权包含不同少数携带者生存的频道区域的装置和方法公开(公告)号：US20130043505A1
公开(公告)日：2013-02-21
申请号：US13211033
申请日：2011-08-16
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/1054 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.
摘要翻译： 示出了诸如存储器件，存储器单元串和电子系统的装置以及形成这种装置的方法。 一种这样的装置包括在一个或多个端部处具有比在中间部分中具有较低的少数载流子寿命的沟道区域。 还公开了其它装置和方法。
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公开(公告)号：US20110134697A1
公开(公告)日：2011-06-09
申请号：US12630332
申请日：2009-12-03
申请人： Yijie Zhao , Akira Goda , Jian Li , Haitao Liu
发明人： Yijie Zhao , Akira Goda , Jian Li , Haitao Liu
CPC分类号： G11C11/5642 , G11C16/26 , G11C16/3418
摘要： Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass voltage is reduced on the adjacent memory cell. The adjacent memory cell can be on the drain side, the source side, or both drain and source sides of the selected memory cell.
摘要翻译： 公开了用于感测和存储器件的方法。 用于感测的一种这样的方法在与选定的存储器单元相邻的至少一个相邻存储器单元上使用动态通过电压用于编程。 如果相邻存储单元未编程，则相邻存储单元上的通过电压降低。 相邻的存储单元可以在所选存储单元的漏极侧，源极侧或漏极和源极侧。
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6.发明授权Memory devices and methods of operating memory devices including applying a potential to a source and a select gate between the source and a string of memory cells while performing a program operation on a memory cell in the string 有权存储器件和操作存储器件的方法包括在源和存储器单元串之间向源和选择栅极施加电位，同时对字符串中的存储器单元执行编程操作公开(公告)号：US09251907B2
公开(公告)日：2016-02-02
申请号：US13438331
申请日：2012-04-03
申请人： Akira Goda , Yijie Zhao , Krishna Parat
发明人： Akira Goda , Yijie Zhao , Krishna Parat
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells.
摘要翻译： 存储器件中的偏置的装置，系统和方法促进存储器件编程和/或擦除操作。 在至少一个实施例中，包括所选择的存储器单元和第二存储单元串的存储器单元的第一串被耦合到公共数据线和公共源，其中数据线和源被偏置到基本上相同的电位 对一个或多个存储器单元串执行编程和/或擦除操作。
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7.发明授权Apparatuses and methods comprising a channel region having different minority carrier lifetimes 有权装置和方法包括具有不同少数载体寿命的通道区域公开(公告)号：US08742481B2
公开(公告)日：2014-06-03
申请号：US13211033
申请日：2011-08-16
IPC分类号： H01L27/108
CPC分类号： H01L29/1054 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.
摘要翻译： 示出了诸如存储器件，存储器单元串和电子系统的装置以及形成这种装置的方法。 一种这样的装置包括在一个或多个端部处具有比在中间部分中具有较低的少数载流子寿命的沟道区域。 还公开了其它装置和方法。
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公开(公告)号：US20110194352A1
公开(公告)日：2011-08-11
申请号：US12702948
申请日：2010-02-09
申请人： Yijie Zhao , Akira Goda
发明人： Yijie Zhao , Akira Goda
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3454
摘要： Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.
摘要翻译： 公开了用于存储器的存储器件和编程方法，诸如适于使用用于编程的第一部分的增加的沟道电压对存储器进行编程的那些，以及用于第二部分编程的增加但是减小的沟道电压。
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公开(公告)号：US08982631B2
公开(公告)日：2015-03-17
申请号：US12702948
申请日：2010-02-09
申请人： Yijie Zhao , Akira Goda
发明人： Yijie Zhao , Akira Goda
CPC分类号： G11C16/12 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3454
摘要： Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.
摘要翻译： 公开了用于存储器的存储器件和编程方法，诸如适于使用用于编程的第一部分的增加的沟道电压对存储器进行编程的那些，以及用于第二部分编程的增加但是减小的沟道电压。
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公开(公告)号：US20130258781A1
公开(公告)日：2013-10-03
申请号：US13438331
申请日：2012-04-03
申请人： Akira Goda , Yijie Zhao , Krishna Parat
发明人： Akira Goda , Yijie Zhao , Krishna Parat
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells.
摘要翻译： 存储器件中的偏置的装置，系统和方法促进存储器件编程和/或擦除操作。 在至少一个实施例中，包括所选择的存储器单元和第二存储单元串的存储器单元的第一串被耦合到公共数据线和公共源，其中数据线和源被偏置到基本上相同的电位 对一个或多个存储器单元串执行编程和/或擦除操作。
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