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31 条记录 (耗时 0.019 秒)

    SENSE OPERATION IN A MEMORY DEVICE
    1.
    发明申请
    SENSE OPERATION IN A MEMORY DEVICE 有权
    在存储器件中的感测操作

    公开(公告)号：US20120182797A1

    公开(公告)日：2012-07-19

    申请号：US13009540

    申请日：2011-01-19

    申请人： Yijie Zhao ,  Akira Goda ,  Mark A. Helm

    发明人： Yijie Zhao ,  Akira Goda ,  Mark A. Helm

    IPC分类号： G11C16/04

    CPC分类号： G11C16/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3422 ,  G11C2211/5641

    摘要： Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.

    摘要翻译： 公开了用于感测和存储器件的方法。 一种用于感测的方法确定与要感测的m位存储器单元相邻的n位存储器单元的阈值电压。 要感测的m位存储器单元的控制栅极利用响应于所确定的n位存储单元的阈值电压而调整的感测电压进行偏置。

    Sense operation in a memory device
    2.
    发明授权
    Sense operation in a memory device 有权
    存储设备中的感应操作

    公开(公告)号：US08374028B2

    公开(公告)日：2013-02-12

    申请号：US13009540

    申请日：2011-01-19

    申请人： Yijie Zhao ,  Akira Goda ,  Mark A. Helm

    发明人： Yijie Zhao ,  Akira Goda ,  Mark A. Helm

    IPC分类号： G11C16/00

    CPC分类号： G11C16/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3422 ,  G11C2211/5641

    摘要： Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.

    摘要翻译： 公开了用于感测和存储器件的方法。 一种用于感测的方法确定与要感测的m位存储器单元相邻的n位存储器单元的阈值电压。 要感测的m位存储器单元的控制栅极利用响应于所确定的n位存储单元的阈值电压而调整的感测电压进行偏置。

    REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE
    3.
    发明申请
    REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE 有权
    减少存储器件中擦除干扰的影响

    公开(公告)号：US20110128782A1

    公开(公告)日：2011-06-02

    申请号：US12628522

    申请日：2009-12-01

    申请人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

    发明人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

    IPC分类号： G11C7/00 ,  G11C16/10

    CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/14

    摘要： Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.

    摘要翻译： 公开了用于编程和存储器件的方法。 一种用于编程的方法包括：初始地利用负电压偏置存储器单元串的多个控制栅极的子集，其中该子集小于该串的多个控制栅极的全部。 在编程阶段期间，所选择的存储单元的控制栅随后用编程电压进行偏置。

    Reducing effects of erase disturb in a memory device
    5.
    发明授权
    Reducing effects of erase disturb in a memory device 有权
    减少存储器件中擦除干扰的影响

    公开(公告)号：US08203876B2

    公开(公告)日：2012-06-19

    申请号：US12628522

    申请日：2009-12-01

    申请人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

    发明人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/14

    摘要： Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.

    摘要翻译： 公开了用于编程和存储器件的方法。 一种用于编程的方法包括：初始地利用负电压偏置存储器单元串的多个控制栅极的子集，其中该子集小于该串的多个控制栅极的全部。 在编程阶段期间，所选择的存储单元的控制栅随后用编程电压进行偏置。

    MEMORY DEVICES AND OPERATING METHODS FOR A MEMORY DEVICE
    7.
    发明申请
    MEMORY DEVICES AND OPERATING METHODS FOR A MEMORY DEVICE 有权
    用于存储器件的存储器件和操作方法

    公开(公告)号：US20140063937A1

    公开(公告)日：2014-03-06

    申请号：US13599208

    申请日：2012-08-30

    申请人： Matthew Goldman ,  Mark A. Helm ,  Jaydip B. Patel ,  Thomas F. Ryan

    发明人： Matthew Goldman ,  Mark A. Helm ,  Jaydip B. Patel ,  Thomas F. Ryan

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5622 ,  G11C2211/5641

    摘要： Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.

    摘要翻译： 器件和方法便于存储器件在所有位线架构存储器件中的操作。 在至少一个实施例中，包括交替行的存储器单元同时由行编程并以第一密度由行同时感测，而包括不同交替行的存储单元同时由行编程并以第二密度由行同时检测。 在至少一个附加实施例中，包括交替层次的存储器单元的存储器单元以第一密度的层被编程和感测，并且包括不同交替层的存储器单元的存储单元由第二密度的层编程和感测。

    Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array
    9.
    发明授权
    Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array 有权
    形成FLASH场效应晶体管阵列和这种阵列外围电路的方法

    公开(公告)号：US06746921B2

    公开(公告)日：2004-06-08

    申请号：US10179893

    申请日：2002-06-24

    申请人： Roger W Lindsay ,  Mark A. Helm

    发明人： Roger W Lindsay ,  Mark A. Helm

    IPC分类号： H01L21336

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

    摘要： Thermal oxidation of a peripheral area of a semiconductor substrate is globally restricted with an overlying oxidation resistant layer that is not globally received within the array during formation of a sacrificial oxide layer prior to forming any transistor gate dielectric layer within the array. At least some FLASH field effect transistor gates having floating gate dielectric of a first thickness are formed within the array and at least some non-FLASH field effect transistor gates having gate dielectric of a second thickness are formed within the periphery, with the first and second thicknesses being different. Other aspects and implementations are disclosed.

    摘要翻译： 在形成阵列内的任何晶体管栅极电介质层之前，在形成牺牲氧化物层期间，覆盖抗氧化层在阵列内未被全局接收的情况下，全局限制半导体衬底的外围区域的热氧化。 至少一些具有第一厚度的浮置栅极电介质的FLASH场效应晶体管栅极形成在阵列内，并且至少一些具有第二厚度的栅极电介质的非FLASH场效应晶体管栅极形成在外围，其中第一和第二 厚度不同。 公开了其他方面和实现。

    Efficient fabrication process for dual well type structures
    10.
    发明授权
    Efficient fabrication process for dual well type structures 失效
    双井型结构的高效制造工艺

    公开(公告)号：US06396100B2

    公开(公告)日：2002-05-28

    申请号：US09901035

    申请日：2001-07-10

    申请人： Mark A. Helm

    发明人： Mark A. Helm

    IPC分类号： H01L29788

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L21/823892

    摘要： An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.

    摘要翻译： 用于制造双井型结构的有效方法使用在单井型结构制造中使用的相同数量的掩模。 在优选实施例中，本发明允许在单个衬底中形成低电压和高电压n沟道晶体管，并且低电压和高压p沟道晶体管形成。 用于形成扩散阱的一个掩模，用于形成逆行阱并掺杂阱以在该阱中实现中间阈值电压的第二掩模，以及用于区分低电压器件的栅极氧化物和掺杂的第三掩模 阈值电压以达到最终阈值电压。