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公开(公告)号：US20120286329A1
公开(公告)日：2012-11-15
申请号：US13106900
申请日：2011-05-13
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： A method and a structure are disclosed relating to strained body UTSOI FET devices. The method includes forming voids in the source/drain regions that penetrate down into the substrate below the insulating layer. The voids are epitaxially filled with a semiconductor material of a differing lattice constant than the one of the SOI layer, thus becoming a stressor block, and imparts a strain onto the FET device body.
摘要翻译： 公开了与应变体UTSOI FET器件有关的方法和结构。 该方法包括在源极/漏极区域中形成穿透绝缘层下方的衬底中的空隙。 空隙被外延填充有与SOI层不同的晶格常数的半导体材料，因此成为应力块，并且在FET器件本体上施加应变。
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公开(公告)号：US20120276695A1
公开(公告)日：2012-11-01
申请号：US13098352
申请日：2011-04-29
IPC分类号： H01L21/8238
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845
摘要： A method is disclosed which is characterized as being process integration of raised source/drain and strained body for ultra thin planar and FinFET CMOS devices. NFET and PFET devices have their source/drain raised by selective epitaxy with in-situ p-type doped SiGe for the PFET device, and in-situ n-type doped Si:C for the NFET device. Such raised source/drains offer low parasitic resistance and they impart a strain onto the device bodies of the correct sign for respective carrier, electron or hole, mobility enhancement.
摘要翻译： 公开了一种方法，其特征在于用于超薄平面和FinFET CMOS器件的凸起源极/漏极和应变体的处理集成。 NFET和PFET器件通过用于PFET器件的原位p型掺杂SiGe的选择性外延以及用于NFET器件的原位n型掺杂Si：C来提高其源极/漏极。 这种升高的源极/漏极提供低的寄生电阻，并且它们对于相应的载流子，电子或空穴，迁移率增强赋予了正确符号的器件体上的应变。
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公开(公告)号：US20120267722A1
公开(公告)日：2012-10-25
申请号：US13540801
申请日：2012-07-03
IPC分类号： H01L27/088
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。
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公开(公告)号：US20110309445A1
公开(公告)日：2011-12-22
申请号：US12816697
申请日：2010-06-16
CPC分类号： H01L29/66045 , H01L21/26506 , H01L21/84 , H01L27/105 , H01L27/1203 , H01L29/6656 , H01L29/66628 , H01L29/66659
摘要： Embodiments of the present invention provide the ability to fabricate devices having similar physical dimensions, yet with different operating characteristics due to the different effective channel lengths. The effective channel length is controlled by forming an abrupt junction at the boundary of the gate and at least one source or drain. The abrupt junction impacts the diffusion during an anneal process, which in turn controls the effective channel length, allowing physically similar devices on the same chip to have different operating characteristics.
摘要翻译： 本发明的实施例提供了制造具有类似物理尺寸但由于不同有效通道长度而具有不同操作特性的装置的能力。 通过在栅极和至少一个源极或漏极的边界处形成突变结点来控制有效沟道长度。 突变结在退火过程中影响扩散，这又控制有效沟道长度，允许同一芯片上物理上相似的器件具有不同的工作特性。
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公开(公告)号：US20110284967A1
公开(公告)日：2011-11-24
申请号：US12786397
申请日：2010-05-24
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/7843 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L2029/7858
摘要： A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.
摘要翻译： 公开了一种用于制造FET器件的方法。 该方法包括具有由第一材料构成的翅片的Fin-FET器件，然后通过外延沉积第二材料而合并在一起。 翅片是使用选择性蚀刻的垂直凹部。 在第一材料和第二材料的增加的表面积上形成连续的硅化物层，导致较小的电阻。 覆盖FET器件的应力衬垫之后被沉积。 还公开了一种FET器件，该FET器件包括多个Fin-FET器件，其翅片由第一材料构成。 FET器件包括第二材料，其外延地融合鳍片。 翅片相对于第二材料的上表面垂直凹入。 FET器件还包括形成在鳍片上方和第二材料上的连续硅化物层，以及覆盖该器件的应力衬垫。
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公开(公告)号：US08785273B2
公开(公告)日：2014-07-22
申请号：US13444219
申请日：2012-04-11
IPC分类号： H01L21/8242 , H01L21/8234
CPC分类号： H01L21/823431 , H01L21/28273 , H01L21/28282 , H01L21/845 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1157 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer.
摘要翻译： 一种制造FinFET非易失性存储器件和FinFET非易失性存储器件结构的方法。 提供衬底并且在衬底上沉积半导体材料层。 在半导体材料上沉积硬掩模，并且将该结构图案化以形成翅片。 电荷存储层沉积在结构上，包括鳍片，并且其部分使用成角度的离子注入工艺被损坏。 损坏的部分被去除并且栅极结构形成在翅片的任一侧，只有一侧具有电荷存储层。
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公开(公告)号：US08742508B2
公开(公告)日：2014-06-03
申请号：US13184537
申请日：2011-07-16
IPC分类号： H01L21/70
CPC分类号： H01L21/28 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7854
摘要： A three dimensional FET device structure which includes a plurality of three dimensional FET devices. Each of the three dimensional FET devices include an insulating base, a three dimensional fin oriented perpendicular to the insulating base, a gate dielectric wrapped around the three dimensional fin and a gate wrapped around the gate dielectric and extending perpendicularly to the three dimensional fin, the three dimensional fin having a device width being defined as the circumference of the three dimensional fin in contact with the gate dielectric. At least a first of the three dimensional FET devices has a first device width while at least a second of the three dimensional FET devices has a second device width. The first device width is different than the second device width. Also included is a method of making the three dimensional FET device structure.
摘要翻译： 一种三维FET器件结构，其包括多个三维FET器件。 三维FET器件中的每一个包括绝缘基底，垂直于绝缘基底取向的三维鳍片，围绕三维翅片缠绕的栅极电介质和围绕栅极电介质缠绕并垂直于三维翅片延伸的栅极， 具有将器件宽度定义为与栅极电介质接触的三维鳍片的圆周的三维鳍片。 三维FET器件中的至少一个具有第一器件宽度，而三维FET器件中的至少一个具有第二器件宽度。 第一个设备宽度与第二个设备宽度不同。 还包括制造三维FET器件结构的方法。
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88.发明授权Method to reduce ground-plane poisoning of extremely-thin SOI (ETSOI) layer with thin buried oxide 有权减少具有薄埋层氧化物的极薄SOI（ETSOI）层的接地面中毒的方法公开(公告)号：US08618554B2
公开(公告)日：2013-12-31
申请号：US12941771
申请日：2010-11-08
IPC分类号： H01L29/15
CPC分类号： H01L29/78603 , H01L21/76254
摘要： The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer.
摘要翻译： 涉及超薄体BOX和双BOX完全耗尽的SOI器件的本公开内容，以及制造这些器件的方法，其具有外延扩散延迟半导体层，其减缓掺杂剂扩散到SOI沟道中。 具有在衬底和SOI沟道之间的外延扩散延迟半导体层的本公开的器件的SOI沟道中的掺杂剂浓度比在没有外延扩散延迟半导体层的器件的SOI沟道中测量的掺杂剂浓度大约小50倍 。
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公开(公告)号：US08586439B1
公开(公告)日：2013-11-19
申请号：US13546150
申请日：2012-07-11
IPC分类号： H01L21/336
CPC分类号： H01L29/93 , H01L27/1203 , H01L29/66174
摘要： In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.
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公开(公告)号：US20130175594A1
公开(公告)日：2013-07-11
申请号：US13551714
申请日：2012-07-18
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1108 , H01L27/1116 , H01L27/1203 , H01L29/945
摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
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