公开(公告)号：US6066530A

公开(公告)日：2000-05-23

申请号：US57992

申请日：1998-04-09

申请人： Michael K. Templeton ,  Kathleen R. Early

发明人： Michael K. Templeton ,  Kathleen R. Early

IPC分类号： H01L21/8247 ,  H01L21/336

CPC分类号： H01L27/11521

摘要： A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O.sub.2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions. After removing the silicon nitride layer portions, and exposing the polysilicon layer portions, the implanted structure is annealed and made ready for forming the self-aligned floating gate MOS structures, or other semiconductor structure on the conductive material pads. The floating gates may be formed having a minimal width with respect to an underlying active region.

摘要翻译： 一种半导体装置和制造方法，用于在用于形成自对准的浮置栅极MOS结构或其它半导体器件的半导体衬底中形成氧化物隔离区。 该方法包括提供预制的半导体衬底构件，其具有制造在多晶硅层上的阻挡氧化物层，多晶硅层和多个间隔开的氮化硅层部分。 氮化物层部分描绘用于形成自对准浮置栅极MOS结构的区域，以及描绘未被多个氮化硅层部分保护的二氧化硅层的部分和所述多晶硅层的部分。 该方法还包括将氧O 2离子注入到衬底的区域中的步骤，包括二氧化硅层的那些未受保护的部分和多晶硅层的部分以形成氧化物隔离区。 在去除氮化硅层部分并暴露多晶硅层部分之后，将注入结构退火并准备好在导电材料焊盘上形成自对准浮栅MOS结构或其它半导体结构。 浮动栅极可以形成为相对于下面的有源区域具有最小宽度。

公开(公告)号：US06834158B1

公开(公告)日：2004-12-21

申请号：US09951473

申请日：2001-09-13

申请人： Michael K. Templeton

发明人： Michael K. Templeton

IPC分类号： F26B330

CPC分类号： B82Y15/00 ,  G03F7/40

摘要： According to one aspect of the present invention, pinhole defects in resist coatings are repaired by heating the resist briefly to induce the resist to flow and fill pinholes. The resist is brought to a temperature at or above that at which the resist flows for long enough to permit the resist to flow and fill pinhole defects, but not so long as to corrupt the resist pattern. The original resist pattern may be biased to allow for some flow during the pinhole repair process. The entire patterned resist may be heated at once, or it may be heated one portion at a time. The application of heat may optionally be limited to locations where pinhole defects are found. By means of the invention, very thin patterned resist coatings free from pinhole defects may be obtained.

摘要翻译： 根据本发明的一个方面，抗蚀剂涂层中的针孔缺陷通过短暂加热抗蚀剂来引起抗蚀剂流动和填充针孔而被修复。 使抗蚀剂达到等于或高于抗蚀剂流动的温度足够长以允许抗蚀剂流动并填充针孔缺陷，但不会损坏抗蚀剂图案。 原始抗蚀剂图案可能被偏压以允许针孔修复过程中的一些流动。 整个图案化的抗蚀剂可以一次加热，或者可以一次加热一部分。 热的应用可以可选地限于找到针孔缺陷的位置。 通过本发明，可以获得非常薄的图案化抗蚀剂涂层，其不存在针孔缺陷。

公开(公告)号：US06830389B2

公开(公告)日：2004-12-14

申请号：US09973034

申请日：2001-10-09

申请人： Michael K. Templeton

发明人： Michael K. Templeton

IPC分类号： G03B500

CPC分类号： G03F7/3007

摘要： A system and method is provided for applying a developer to a photoresist material layer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a apertures for dispensing developer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap. A differential voltage is applied to the developer plate and the wafer causing an electric field to be formed in the gap. Transportation of negatively charge photoresist material is facilitated by exposure to the electric field during the development process.

摘要翻译： 提供了一种用于将显影剂施加到设置在半导体衬底上的光致抗蚀剂材料层的系统和方法。 显影剂系统和方法采用具有多个用于分配显影剂的孔的显影剂板。 优选地，显影剂板具有与晶片类似的形状的底表面。 显影剂板设置在晶片上方并且在施加显影剂的过程中基本上和/或完全地包围晶片的顶表面。 在晶片和显影剂板的底表面之间形成小的间隙。 晶片和显影剂板形成平行板对，使得间隙可以制得足够小，使得显影剂流体快速填充间隙。 对显影剂板和晶片施加差分电压，从而在间隙中形成电场。 在显影过程中通过暴露于电场来促进负电荷光致抗蚀剂材料的传输。

公开(公告)号：US6110833A

公开(公告)日：2000-08-29

申请号：US33836

申请日：1998-03-03

申请人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

发明人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

IPC分类号： A61K38/00 ,  A61K38/30 ,  H01L21/8247 ,  H01L21/70

CPC分类号： H01L27/11521 ,  A61K38/30

摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.

摘要翻译： 提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。 蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。 绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙 第二存储单元。 此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。

公开(公告)号：US6043120A

公开(公告)日：2000-03-28

申请号：US33723

申请日：1998-03-03

申请人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

发明人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.

摘要翻译： 一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 在多晶硅层上沉积或生长掩模层，并且蚀刻掩模层的至少一部分，以便对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极电隔离。 在多层I层和绝缘体上形成多层介电层和第二多晶硅（poly II）层，绝缘体基本上没有台阶高度的突然变化。

公开(公告)号：US5920786A

公开(公告)日：1999-07-06

申请号：US60894

申请日：1998-05-14

申请人： Tuan D. Pham ,  Michael K. Templeton

发明人： Tuan D. Pham ,  Michael K. Templeton

IPC分类号： G03F7/00 ,  G03F7/20 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762 ,  H01L29/68 ,  G03C5/00 ,  G03F9/00

CPC分类号： H01L21/3086 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/3065 ,  H01L21/76232

摘要： The present invention provides a method of constructing trenches for use in microelectronic circuit structures. A photolithographic method is used to create trenches with sloped walls shaping the photoresist masks into sloped profiles. These photoresist masks effectively shape the underlying substrate during subsequent etch steps producing sloped wall trenches. These trenches can be used as shallow trench isolation structures to isolate microelectronic circuit structures from each other.

摘要翻译： 本发明提供一种构建用于微电子电路结构的沟槽的方法。 使用光刻方法来产生具有将光致抗蚀剂掩模成形为倾斜轮廓的倾斜壁的沟槽。 这些光致抗蚀剂掩模在随后的蚀刻步骤中有效地塑造下面的衬底，产生倾斜的壁沟槽。 这些沟槽可以用作浅沟槽隔离结构，以隔离微电子电路结构。

公开(公告)号：US06688784B1

公开(公告)日：2004-02-10

申请号：US09974620

申请日：2001-10-10

申请人： Michael K. Templeton

发明人： Michael K. Templeton

IPC分类号： G03D504

CPC分类号： G03D5/04 ,  Y10S134/902

摘要： A system and method is provided for applying a developer to a photoresist material layer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a application apertures for dispensing developer and a plurality of exit apertures for allowing excess developer to be removed from between the developer plate and the photoresist material layer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap with excess developer exiting through the exit apertures.

摘要翻译： 提供了一种用于将显影剂施加到设置在半导体衬底上的光致抗蚀剂材料层的系统和方法。 显影剂系统和方法采用具有多个用于分配显影剂的施加孔的显影剂板和用于允许从显影剂板和光致抗蚀剂材料层之间移除多余显影剂的多个出口孔的显影剂板。 优选地，显影剂板具有与晶片类似的形状的底表面。 显影剂板设置在晶片上方并且在施加显影剂的过程中基本上和/或完全地包围晶片的顶表面。 在晶片和显影剂板的底表面之间形成小的间隙。 晶片和显影剂板形成平行板对，使得间隙可以制得足够小，使得显影剂流体通过出射孔离开的过量显影剂快速填充间隙。

公开(公告)号：US06664191B1

公开(公告)日：2003-12-16

申请号：US09973131

申请日：2001-10-09

申请人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

发明人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

IPC分类号： H01L21302

CPC分类号： H01L27/11526 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76229 ,  H01L21/76838 ,  H01L27/11531 ,  Y10S438/975

摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.

摘要翻译： 提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。 在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。 第一多晶硅层沉积在覆盖STI区域的衬底上。 然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。 在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。 在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。 氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

公开(公告)号：US06455888B1

公开(公告)日：2002-09-24

申请号：US09506298

申请日：2000-02-17

申请人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

发明人： Kathleen R. Early ,  Michael K. Templeton ,  Nicholas H. Tripsas ,  Maria C. Chan

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  A61K38/30

摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.

摘要翻译： 提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。 在氧化物涂覆的基底上形成第一多晶硅（poly I）层。 然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。 蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。 多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。 绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙 第二存储单元。 此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。

公开(公告)号：US06423475B1

公开(公告)日：2002-07-23

申请号：US09266367

申请日：1999-03-11

申请人： Christopher F. Lyons ,  Michael K. Templeton ,  Kathleen R. Early

发明人： Christopher F. Lyons ,  Michael K. Templeton ,  Kathleen R. Early

IPC分类号： G03C500

CPC分类号： H01L21/32139

摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a photoresist over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the photoresist having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the photoresist, the sidewall film having a vertical portion adjacent the sidewall of the photoresist and a horizontal portion in areas not adjacent the sidewall of the photoresist; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the photoresist exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.

摘要翻译： 在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在所述导电膜的第一部分上图案化光致抗蚀剂，其中所述导电膜的第二部分被暴露，所述光致抗蚀剂在所述导电膜上具有至少一个侧壁; 在所述导电膜和所述光致抗蚀剂上沉积侧壁膜，所述侧壁膜具有邻近所述光致抗蚀剂的侧壁的垂直部分和在不邻近所述光致抗蚀剂的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 去除暴露导电膜的第四部分的光致抗蚀剂; 并且蚀刻导电膜的第三部分和第四部分，从而提供具有约100nm或更小的宽度在该侧壁膜的垂直部分下方的导电结构。