Abstract:
An ultra-large scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs utilize gate structures with heavily doped polysilicon and germanium material. The polysilicon and germanium materials or thin films are manufactured by low pressure chemical vapor deposition. A silicon buffer layer and oxide cap is used to prevent germanium outgassing.
Abstract:
A coupling capacitor is coupled between the gate and the body region of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The body region of the MOSFET is electrically isolated to form a floating body region. The capacitance of the coupling capacitor is designed such that a BJT (Bipolar Junction Transistor) connected in parallel with the MOSFET turns on when the MOSFET turns on. In addition such a design of the coupling capacitor lowers the magnitude of the threshold voltage of the MOSFET when the MOSFET is turned on. Furthermore, the capacitance of the coupling capacitor is designed such that the magnitude of the threshold voltage of the MOSFET is raised when the MOSFET is turned off. Thus, the MOSFET type device of the present invention has both higher drive current when the MOSFET is turned on and lower steady state power dissipation when the MOSFET is turned off with a variable threshold voltage.
Abstract:
A method of performing tilted implantation for pocket, halo and source/drain extensions in ULSI dense structures. The method overcomes the process limit, due to shadowing effects, in dense structures, of using large angle tilted implant techniques in ULSI circuits. A gate opening in an oxide layer is defined and partially filled by insertion of nitride spacers to define an actual gate window opening. The small angle tilted implant technique has the equivalent doping effect of large angle tilted implants, and circumvents the maximum angle limit (&thgr;MAX) that occurs in the large angle implant method. The small angle tilted implant technique also automatically provides self alignment of the pocket/halo/extension implant to the gate of the device.
Abstract:
An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs are provided on an SOI substrate. The thickness of a thin film on the substrate is varied to adjust the threshold voltage. The threshold voltage can be varied by roughly 240 mV. The thickness of the thin film can be adjusted through a LOCOS process.
Abstract:
A method of fabricating an integrated circuit with ultra-shallow source and drain junctions utilizes a dummy or sacrificial gate spacer. Ions are implanted and dopants are provided through the openings associated with sacrificial spacers to form the source and drain extensions. The openings can be filled with an insulative layer. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETS).
Abstract:
An ultra-low thermal budget process is provided for channel implant by using a reverse process sequence where a conventional MOS transistor is formed without the channel implant. The originally deposited polysilicon gate is removed, a nitride film deposition and etch is used to form a nitride spacer with a predetermined configuration, and a self-aligned channel implant is performed. After the channel implantation, anneal and super-retrograded doping, the nitride spacer and the gate oxide are removed for subsequent regrowth of a second gate oxide and a polysilicon deposition to form a second polysilicon gate.
Abstract:
A method for making a ULSI MOSFET includes establishing a void in a field oxide layer on a silicon substrate and filling the center of the void with a gate electrode. A high-k gate insulator is sandwiched between the gate electrode and the substrate. Around the void, a low-k gate spacer is formed, with the gate spacer being disposed directly above the source and drain extensions of the MOSFET.
Abstract:
A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions and central conductive portion. The edge conductive portions provide high potential barriers against the active regions, thereby reducing threshold voltage roll off and leakage current.
Abstract:
The present invention relates to methods for cryopreserving plant cells and to methods for recovering viable plant cells from long or short term cryopreservation. Plant cells to be cryopreserved can be grown in culture and pretreated with a solution containing an cryoprotective agent and a stabilizer. Pretreated cells are acclimated to a reduced temperature and loaded with a cryoprotective agent such as DMSO, propylene glycol or polyethylene glycol. Loaded cells are incubated with a vitrification solution which, for example, comprises a solution with a high concentration of the cryoprotective agent. Vitrified cells retain less than about 20% water content and can be frozen at cryopreservation temperatures for long periods of time without significantly altering the genotypic or phenotypic character of the cells. Plant cells may also be cryopreserved by lyophilizing cells prior to exposure to a vitrification solution. The combination of lyophilization and vitrification removes about 80% to about 95% of the plant cell's water. Cells can be successfully cryopreserved for long periods of time and viably recovered. The invention also relates to methods for the recovery of viable plant cells from cryopreservation. Cells are thawed to about room temperature and incubated in medium containing a cryoprotective agent and a stabilizer. The cryoprotective agent is removed and the cells successfully incubated and recovered in liquid or semi-solid growth medium. The invention also relates to the cryopreserved cells and to viable plant cells which have been recovered from long or short term cryopreservation.
Abstract:
Disclosed is an aircraft environmental control and fuel tank inerting coupling system based on a membrane separation method. The dehumidification of gas in an aircraft environmental control system and the separation of oxygen and nitrogen in a fuel tank inerting system are realized respectively, based on the selective permeability of a membrane to water vapour/air and oxygen/nitrogen. In the coupling system, part of drying gas passing through a membrane dehumidification heat exchanger (5) enters a membrane air separator (9), and the other part thereof is cooled through a large expansion turbine (8) and then directed into a cockpit for refrigeration; and nitrogen-rich gas generated by the membrane air separator (9) is directed into a fuel tank for inerting. Oxygen-rich gas is mixed with gas supplied by the environmental control system, thus increasing the oxygen content of gas supplied by the aircraft cockpit.