公开(公告)号：US20110237041A1

公开(公告)日：2011-09-29

申请号：US13155957

申请日：2011-06-08

申请人： Chen-Liang Chu ,  Chun-Ting Liao ,  Fei-Yuh Chen ,  Tsung-Yi Huang

发明人： Chen-Liang Chu ,  Chun-Ting Liao ,  Fei-Yuh Chen ,  Tsung-Yi Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.

摘要翻译： 提供半导体器件。 在一个实施例中，该器件包括形成在半导体衬底上的衬底和晶体管。 晶体管可以包括栅极结构，源极区和漏极区。 漏极区域包括交替掺杂分布区域。 交变掺杂剖面区域可以包括掺杂剂的高浓度和低浓度的交替区域。 在一个实施例中，晶体管是高压晶体管。

公开(公告)号：US07928508B2

公开(公告)日：2011-04-19

申请号：US12103524

申请日：2008-04-15

申请人： Chih-Wen (Albert) Yao ,  Puo-Yu Chiang ,  Tsai Chun Lin ,  Tsung-Yi Huang

发明人： Chih-Wen (Albert) Yao ,  Puo-Yu Chiang ,  Tsai Chun Lin ,  Tsung-Yi Huang

IPC分类号： H01L29/66

CPC分类号： H01L29/063 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region; a gate dielectric extending from over the first HVW region to over the second HVW region; a gate electrode on the gate dielectric; a drain region in the second HVW region; a source region at an opposite side of the gate dielectric than the drain region; and a deep well region of the first conductivity type underlying the second HVW region. Substantially no deep well region is formed directly underlying the drain region.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二HVW区域与第一导电类型相反，覆盖在衬底上并横向邻接第一HVW区域; 从第一HVW区域延伸到第二HVW区域上方的栅极电介质; 栅电极上的栅电极; 第二HVW区域中的漏极区域; 栅极电介质的与漏极区相反的一侧的源极区; 以及位于第二HVW区域下方的第一导电类型的深阱区域。 基本上没有深沟区直接形成在漏极区下面。

公开(公告)号：US07888734B2

公开(公告)日：2011-02-15

申请号：US12328277

申请日：2008-12-04

申请人： Chen-Liang Chu ,  Chun-Ting Liao ,  Tsung-Yi Huang ,  Fei-Yuh Chen

发明人： Chen-Liang Chu ,  Chun-Ting Liao ,  Tsung-Yi Huang ,  Fei-Yuh Chen

IPC分类号： H01L29/66

CPC分类号： H01L29/7833 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7835

摘要： An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.

摘要翻译： 集成电路结构包括半导体衬底中的高电压阱（HVW）区域; HVW区域中的第一双扩散（DD）区域; 和HVW区域中的第二DD区域。 第一DD区域和第二DD区域通过HVW区域的中间部分彼此间隔开。 凹部从半导体衬底的顶表面延伸到HVW区域和第二DD区域的中间部分。 栅极电介质延伸到凹部中并覆盖凹部的底部。 栅极电极在栅极电介质上方。 第一源/漏区在第一DD区。 第二个源极/漏极区域位于第二个DD区域。

公开(公告)号：US20110006366A1

公开(公告)日：2011-01-13

申请号：US12887300

申请日：2010-09-21

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L29/78

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

摘要翻译： 半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区 区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极 电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

公开(公告)号：US07816744B2

公开(公告)日：2010-10-19

申请号：US12170133

申请日：2008-07-09

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L29/49

CPC分类号： H01L29/4983 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。 栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。 第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

公开(公告)号：US07816214B2

公开(公告)日：2010-10-19

申请号：US12362307

申请日：2009-01-29

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L21/8234

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

摘要翻译： 半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区 区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极 电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

公开(公告)号：US20100096697A1

公开(公告)日：2010-04-22

申请号：US12256009

申请日：2008-10-22

申请人： Ru-Yi Su ,  Pou-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Pou-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L29/78

CPC分类号： H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7835

摘要： A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底中的源极区和漏极区，形成在衬底上的栅极结构，该衬底设置在源极和漏极区之间，第一隔离结构形成在栅极结构和栅极结构之间的衬底中 漏极区域，所述第一隔离结构包括位于所述漏极区域的边缘附近的突起。 每个突起包括在沿着漏极区域的边缘的第一方向上测量的宽度和在垂直于第一方向的第二方向上测量的长度，并且相邻的突起彼此间隔一定距离。

公开(公告)号：US07423319B2

公开(公告)日：2008-09-09

申请号：US11646683

申请日：2006-12-28

申请人： Robin Hsieh ,  Tsai Chun Lin ,  Albert Yao ,  Pai-Kang Hsu ,  Tsung-Yi Huang ,  Ruey-Hsin Liu

发明人： Robin Hsieh ,  Tsai Chun Lin ,  Albert Yao ,  Pai-Kang Hsu ,  Tsung-Yi Huang ,  Ruey-Hsin Liu

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/66659

摘要： A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.

公开(公告)号：US09362381B2

公开(公告)日：2016-06-07

申请号：US14971496

申请日：2015-12-16

申请人： Chih-Fang Huang ,  Tsung-Yi Huang ,  Chien-Wei Chiu ,  Tsung-Yu Yang ,  Ting-Fu Chang ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  Po-Chin Peng

发明人： Chih-Fang Huang ,  Tsung-Yi Huang ,  Chien-Wei Chiu ,  Tsung-Yu Yang ,  Ting-Fu Chang ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  Po-Chin Peng

IPC分类号： H01L29/66 ,  H01L29/73 ,  H01L29/10 ,  H01L29/20 ,  H01L29/201 ,  H01L27/07

CPC分类号： H01L29/66325 ,  H01L27/0722 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787

摘要： The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.

摘要翻译： 本发明公开了一种绝缘栅双极晶体管（IGBT）及其制造方法。 IGBT包括：氮化镓（GaN）衬底，具有第一导电类型的第一GaN层，具有第一导电类型的第二GaN层，具有第二导电类型或本征导电类型的第三GaN层，以及栅极 形成在GaN衬底上。 第一GaN层形成在GaN衬底上并且具有垂直于GaN衬底的侧壁。 第二GaN层形成在GaN衬底上，并通过栅极与第一GaN层分离。 第三GaN层形成在第一GaN层上，并通过第一GaN层与GaN衬底分离。 门具有在横向方向上与侧壁相邻的侧板以控制通道。

公开(公告)号：US09343538B2

公开(公告)日：2016-05-17

申请号：US13107191

申请日：2011-05-13

申请人： Tsung-Yi Huang

发明人： Tsung-Yi Huang

IPC分类号： H01L29/423 ,  H01L29/06

CPC分类号： H01L29/42368 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66659 ,  H01L29/7835

摘要： A high voltage device includes: a substrate having a first isolation structure to define a device region; a source and a drain in the device region; a gate on the substrate and between the source and the drain; and a second isolation structure. The second isolation structure includes a first isolation region and a second isolation region. The first isolation region is on the substrate and between the source and the drain, and is partially or totally covered by the gate. The second isolation region is in the substrate and below the gate, and has a depth in the substrate which is deeper than the depth of the first isolation region in the substrate, and the length of the second isolation region in a direction along an imaginary line connecting the source and the drain does not exceed one-third length of the first isolation region.

摘要翻译： 高电压装置包括：具有第一隔离结构以限定器件区域的衬底; 设备区域中的源极和漏极; 基板上的栅极和源极与漏极之间的栅极; 和第二隔离结构。 第二隔离结构包括第一隔离区域和第二隔离区域。 第一隔离区域位于基板上，在源极和漏极之间，并且部分或全部被栅极覆盖。 第二隔离区位于衬底中并在栅极下方，并且在衬底中具有比衬底中的第一隔离区的深度更深的深度，以及沿着假想线的方向上的第二隔离区的长度 连接源极和漏极不超过第一隔离区域的三分之一长度。