Methods and apparatus to provide an auxiliary receive path to support transmitter functions
    83.
    发明授权
    Methods and apparatus to provide an auxiliary receive path to support transmitter functions 有权
    提供辅助接收路径以支持发射机功能的方法和装置

    公开(公告)号:US07822389B2

    公开(公告)日:2010-10-26

    申请号:US11595101

    申请日:2006-11-09

    IPC分类号: H04B1/44

    CPC分类号: H04B1/52

    摘要: Methods and apparatus to provide an auxiliary receive path to support transmitter functions are disclosed. An example transceiver includes an antenna and a duplexer coupled to the antenna. A transmitter is coupled to the duplexer to output a transmit signal at a transmit frequency. A receiver is coupled to the duplexer to receive a received signal at a receiver frequency. A signal processor is coupled to the transmitter and receiver. An auxiliary receiver is communicatively coupled to the signal processor to receive the transmit signal output from the transmitter and send an auxiliary receiver signal to the signal processor. The signal processor adjusts the transmit signal based on the auxiliary receiver signal.

    摘要翻译: 公开了提供辅助接收路径以支持发射机功能的方法和装置。 示例收发器包括耦合到天线的天线和双工器。 发射机耦合到双工器以以发射频率输出发射信号。 接收机耦合到双工器以在接收机频率处接收接收的信号。 信号处理器耦合到发射机和接收机。 辅助接收器通信地耦合到信号处理器以接收从发射机输出的发射信号,并向辅助接收机信号发送信号处理器。 信号处理器根据辅助接收机信号调整发射信号。

    Type-II all-digital phase-locked loop (PLL)
    86.
    发明授权
    Type-II all-digital phase-locked loop (PLL) 有权
    II型全数字锁相环(PLL)

    公开(公告)号:US07382200B2

    公开(公告)日:2008-06-03

    申请号:US11464420

    申请日:2006-08-14

    IPC分类号: H03L7/00

    摘要: System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

    摘要翻译: 用于提供具有快速信号采集模式的II型(和更高阶)锁相环(PLL)的系统和方法。 优选实施例包括具有比例环路增益路径(比例环路增益电路1115)和积分环路增益模块(积分环路增益模块1120)的环路滤波器。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽,从而快速获取所需信号的信号。 然后,在PLL的信号跟踪阶段期间,使用积分环路增益模块,并将其输出与比例环路增益路径的输出相结合,以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量,以帮助改善信号跟踪稳定时间。

    On-Chip Receiver Sensitivity Test Mechanism
    87.
    发明申请
    On-Chip Receiver Sensitivity Test Mechanism 有权
    片上接收灵敏度测试机制

    公开(公告)号:US20080042872A1

    公开(公告)日:2008-02-21

    申请号:US11835274

    申请日:2007-08-07

    IPC分类号: G08C15/00

    摘要: An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillators to perform sensitivity testing. Tile on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated. The BER reading is used either externally or by an on-chip processor or controller to establish a pass/fail indication for the chip.

    摘要翻译: 用于集成RF发射机的片上接收机灵敏度测试机构,其中发射机和接收机共享相同的振荡器。 该机构避免了使用具有内置调制能力的昂贵的RF信号发生器测试设备的需要,并且允许使用非常低成本的外部RF测试设备。 本发明利用已经存在于收发器中的电路,即调制电路和本地振荡器来执行灵敏度测试。 瓦片片上LO用于产生调制测试信号,否则将需要由具有调制能力的昂贵的外部RF测试设备提供。 调制的LO信号与外部产生的未调制的CW RF信号混合以在IF处产生调制信号,随后由接收机链的其余部分处理。 恢复的数据位使用片上BER计或计数器进行比较,产生BER读数。 BER读数在外部使用或由片上处理器或控制器用于建立芯片的通过/失败指示。

    Removing close-in interferers through a feedback loop
    88.
    发明授权
    Removing close-in interferers through a feedback loop 有权
    通过反馈回路消除紧密的干扰源

    公开(公告)号:US07218904B2

    公开(公告)日:2007-05-15

    申请号:US10280156

    申请日:2002-10-25

    IPC分类号: H04B1/06 H03F1/26

    CPC分类号: H04B1/28 H04B1/1036

    摘要: System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.

    摘要翻译: 通过反馈消除接近干扰的系统和方法。 优选实施例包括耦合到直接RF无线电接收机(例如,无线电接收机800)的数字输出的干扰源预测器(例如,干扰源预测器840)。 干扰源预测器预测干扰源的存在,并且通过使用电荷共享通过反馈电路(例如,反馈单元845)将信息反馈给采样单元(例如,采样单元805)。 然后在采样单元中消除干扰源。 另外,通过执行任意系数有限脉冲响应滤波器来增加和改变采样单元滤波器中的零数和位置。

    Efficient pulse amplitude modulation transmit modulation
    89.
    发明授权
    Efficient pulse amplitude modulation transmit modulation 有权
    有效的脉冲幅度调制发射调制

    公开(公告)号:US06924681B2

    公开(公告)日:2005-08-02

    申请号:US10154093

    申请日:2002-05-22

    摘要: Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.

    摘要翻译: 由PAM调制器提供有效的PAM发射调制,PAM调制器包括提供时钟信号CKV(408)的振荡器(404)。 时钟信号408和时钟信号的延迟版本(CKV_DLY)420被提供给逻辑门(414)。 逻辑门(414)的输出用作射频功率放大器(416)的功率放大器输入信号(PA_IN)。 根据CKV时钟信号(408)和CKV_DLY延迟时钟信号(420)的相对时间延迟,可以控制逻辑门(414)占空比的定时和占空比。 占空比或脉冲宽度变化影响功率放大器的导通时间(416); 从而建立RF输出振幅。

    Methods and apparatus to control frequency offsets in digitally controlled crystal oscillators
    90.
    发明申请
    Methods and apparatus to control frequency offsets in digitally controlled crystal oscillators 审中-公开
    控制数字控制晶体振荡器频偏的方法和装置

    公开(公告)号:US20050093638A1

    公开(公告)日:2005-05-05

    申请号:US10966220

    申请日:2004-10-15

    CPC分类号: H03L1/026 H03L1/028 H03L7/00

    摘要: Methods and systems of adjusting an oscillator frequency are disclosed. One example method includes reading a temperature associated with an oscillator, reading a first tuning code associated with the temperature from a memory, and tuning the oscillator with the first tuning code. The example method may further include determining a second tuning code, and storing the second tuning code and an indication of the temperature in the memory.

    摘要翻译: 公开了调整振荡器频率的方法和系统。 一个示例性方法包括读取与振荡器相关联的温度,从存储器读取与温度相关联的第一调谐代码,以及用第一调谐代码调谐振荡器。 示例性方法还可以包括确定第二调谐代码,以及将第二调谐代码和温度的指示存储在存储器中。