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127 条记录 (耗时 0.043 秒)

    METHOD OF FORMING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE
    82.
    发明申请
    METHOD OF FORMING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE 有权
    在SOI衬底上形成高性能FET和高电压FET的方法

    公开(公告)号：US20100035390A1

    公开(公告)日：2010-02-11

    申请号：US12188366

    申请日：2008-08-08

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

    IPC分类号： H01L21/84

    CPC分类号： H01L21/84 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1203 ,  H01L27/1207

    摘要： A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.

    摘要翻译： 保护绝缘体上半导体（SOI）衬底的顶部半导体层的第一部分，同时去除顶部半导体层的第二部分以暴露掩埋的绝缘体层。 形成包括位于顶部半导体层的第一部分上方的栅极电介质和栅电极的第一场效应晶体管。 暴露的掩埋绝缘体层的一部分用作第二场效应晶体管的栅极电介质。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。

    METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
    84.
    发明申请
    METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
    用于形成片上高频电静电放电装置的方法

    公开(公告)号：US20090317970A1

    公开(公告)日：2009-12-24

    申请号：US12144089

    申请日：2008-06-23

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/7682 ,  H01L27/0248

    摘要： A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection.

    摘要翻译： 描述了在集成电路上形成片上高频静电放电装置的方法。 在该方法的一个实施例中，提供了一种其上形成有多于一个电极的封盖的第一电介质层。 在封盖的第一介电层上沉积第二介电层。 第一硬掩模介电层沉积在第二介电层上。 通过第一硬掩模电介质层和第二电介质层形成腔沟槽到第一介电层，其中在两个相邻电极之间的第一电介质层中形成空腔沟槽。 至少一个通孔围绕腔沟槽形成穿过第二电介质层。 在所述至少一个通孔中的每一个周围形成金属沟槽。 在空腔沟槽上形成释放开口。 在第二电介质层上沉积第三电介质层，其中第三介电层气密地密封释放开口以提供静电放电保护。

    DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
    85.
    发明申请
    DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 有权
    片上高频电子放电装置的设计结构

    公开(公告)号：US20090316314A1

    公开(公告)日：2009-12-24

    申请号：US12144095

    申请日：2008-06-23

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC分类号： H02H9/00 ,  G06F17/50

    CPC分类号： H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.

    摘要翻译： 描述了片上高频静电放电装置的设计结构。 在一个实施例中，静电放电结构包括其中形成有多于一个电极的第一电介质层。 其中形成有多于一个电极的第二电介质层位于第一介电层的上方。 至少一个通孔将第一介电层中的多于一个的电极与第二介电层中的多于一个的电极连接。 通过第一电介质层和第二电介质层形成间隙，其中间隙在第一电介质层和第二电介质层中的两个相邻电极之间延伸。 第三电介质层设置在第二电介质层上，其中第三介电层气密地密封间隙以在集成电路上提供静电放电保护。

    Vertical LC tank device
    87.
    发明授权
    Vertical LC tank device 失效
    垂直液相色谱槽装置

    公开(公告)号：US07564319B2

    公开(公告)日：2009-07-21

    申请号：US11859850

    申请日：2007-09-24

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

    IPC分类号： H03B5/08 ,  H01F5/00 ,  H01L29/00

    CPC分类号： H03L7/099 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0641 ,  H01L27/08 ,  H01L27/0811 ,  H01L28/10 ,  H01L2924/0002 ,  H03J3/20 ,  H01L2924/00

    摘要： An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.

    摘要翻译： 一种LC粘结结构。 该结构包括在半导体衬底顶部的一组布线级别，从最靠近衬底的最低配线水平到离衬底最远的最高配线电平彼此堆叠的布线电平; 电感处于最高布线水平，电感器限制在最高布线水平的区域的周边内; 以及形成在基板中的变容二极管，变容二极管完全对准在最高布线水平的区域的周边。 该结构可以另外包括在最低布线电平和最高布线电平之间的布线级别的布线级中的电屏蔽。 或者，电感器包括磁芯和交替的非磁性导电金属线圈和围绕磁芯的磁性线圈。

    BURIED SUBCOLLECTOR FOR HIGH FREQUENCY PASSIVE DEVICES
    89.
    发明申请
    BURIED SUBCOLLECTOR FOR HIGH FREQUENCY PASSIVE DEVICES 失效
    用于高频无源器件的BURIED SUBCOLLECTOR

    公开(公告)号：US20070105354A1

    公开(公告)日：2007-05-10

    申请号：US11164108

    申请日：2005-11-10

    申请人： Douglas Coolbaugh ,  Xuefeng Liu ,  Robert Rassel ,  David Sheridan

    发明人： Douglas Coolbaugh ,  Xuefeng Liu ,  Robert Rassel ,  David Sheridan

    IPC分类号： H01L21/425

    CPC分类号： H01L21/8249 ,  H01L29/0821 ,  H01L29/66272

    摘要： A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.

    摘要翻译： 一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。 特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。 该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比） 。 本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。

    SiGe HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) AND METHOD OF FABRICATION
    90.
    发明申请
    SiGe HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) AND METHOD OF FABRICATION 失效
    SiGe异质双极晶体管（HBT）和制造方法

    公开(公告)号：US20060060887A1

    公开(公告)日：2006-03-23

    申请号：US10711482

    申请日：2004-09-21

    申请人： Peter Geiss ,  Alvin Joseph ,  Rajendran Krishnasamy ,  Xuefeng Liu

    发明人： Peter Geiss ,  Alvin Joseph ,  Rajendran Krishnasamy ,  Xuefeng Liu

    IPC分类号： H01L31/109

    CPC分类号： H01L29/66242 ,  H01L29/7378

    摘要： A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.

    摘要翻译： 在包括集电极区域的第一导电类型的半导体衬底中形成异质结双极晶体管。 在基板上形成基极区域，在基极区域上形成发射极区域。 集电极，基极和发射极区域中的至少一个包括掺杂有第一浓度的杂质的第一区域和掺杂有第二浓度的杂质的第二区域。 提高异质结双极晶体管的噪声性能和可靠性，而不会降低交流性能。