公开(公告)号：US07045873B2

公开(公告)日：2006-05-16

申请号：US10728750

申请日：2003-12-08

申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Geng Wang

IPC分类号： H01L29/00

CPC分类号： H01L29/783

摘要： Provision of a body control contact adjacent a transistor and between the transistor and a contact to the substrate or well in which the transistor is formed allows connection and disconnection of the substrate of the transistor to and from a zero (ground) or substantially arbitrary low voltage in accordance with control signals applied to the gate of the transistor to cause the transistor to exhibit a variable threshold which maintains good performance at low supply voltages and reduces power consumption/dissipation which is particularly advantageous in portable electronic devices. Floating body effects (when the transistor substrate in disconnected from a voltage source in the “on” state) are avoided since the substrate is discharged when the transistor is switched to the “off” state. The transistor configuration can be employed with both n-type and p-type transistors which may be in complementary pairs.

摘要翻译： 提供与晶体管相邻并且晶体管与形成晶体管的衬底或阱的接触之间的身体控制接触允许晶体管的衬底与零（接地）或基本上任意的低电压的连接和断开 根据施加到晶体管的栅极的控制信号，使晶体管呈现可变阈值，其在低电源电压下保持良好的性能，并降低了在便携式电子设备中特别有利的功耗/耗散。 避免浮体效应（当晶体管基板与电压源处于“导通”状态断开时），因为当晶体管切换到“关闭”状态时，衬底被放电。 晶体管配置可以与可以互补对的n型和p型晶体管一起使用。

公开(公告)号：US20050062161A1

公开(公告)日：2005-03-24

申请号：US10605308

申请日：2003-09-22

申请人： Xiangdong Chen ,  Li Wang

发明人： Xiangdong Chen ,  Li Wang

IPC分类号： H01L21/60 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L23/48

CPC分类号： H01L27/10888 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10861 ,  H01L27/10873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method are provided for a conductor line stack of an integrated circuit. The conductor line stack includes a layer of a first material such as heavily doped polysilicon or a metal silicide. A layer of a second material such as a metal is formed over the layer of first material, the layer of second material having an upper portion and a lower portion. A pair of first spacers is disposed on sidewalls of the upper portion, wherein the lower portion has width defined by a combined width of the upper portion and the pair of first spacers. A pair of second spacers is formed on sidewalls of the first spacers, the lower portion and the layer of first material. The conductor line stack structure is well adapted for formation of a borderless bitline contact in contact therewith.

摘要翻译： 为集成电路的导线堆叠提供了一种结构和方法。 导线堆叠包括第一材料层，例如重掺杂多晶硅或金属硅化物。 在第一材料层上形成诸如金属的第二材料层，第二材料层具有上部和下部。 一对第一间隔件设置在上部的侧壁上，其中下部具有由上部和第一对间隔件的组合宽度限定的宽度。 在第一间隔件，下部和第一材料层的侧壁上形成一对第二间隔件。 导体线堆叠结构很好地适于形成与其接触的无边界位线接触。

公开(公告)号：US09548251B2

公开(公告)日：2017-01-17

申请号：US13349045

申请日：2012-01-12

申请人： Rezaur Rahman Khan ,  Sam Ziqun Zhao ,  Pieter Vorenkamp ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Xiangdong Chen

发明人： Rezaur Rahman Khan ,  Sam Ziqun Zhao ,  Pieter Vorenkamp ,  Kevin Kunzhong Hu ,  Sampath K. V. Karikalan ,  Xiangdong Chen

IPC分类号： H01L23/48 ,  H01L23/13 ,  H01L25/065 ,  H01L23/498

CPC分类号： H01L23/13 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157

摘要： A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

摘要翻译： 半导体封装可以包括衬底和具有空腔和多个通孔半导体通孔的半导体插入器。 半导体插入器位于衬底上。 插入式管芯设置在半导体插入器的空腔内。 导热粘合剂设置在空腔内并与内插器模具接触。 此外，顶部管芯位于半导体插入器上方。 在一个实现中，半导体插入器是硅插入器。 在另一个实施方式中，将半导体插入器倒装芯片安装到基板上，使得设置在空腔内的内插器芯片面向基板。 在又一实施方案中，半导体插入器中的空腔可以从半导体插入器的顶表面延伸到半导体插入器的底表面，并且热界面材料可以设置在内插器管芯和衬底之间。

公开(公告)号：US09129856B2

公开(公告)日：2015-09-08

申请号：US13179248

申请日：2011-07-08

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L27/115 ,  H01L21/8238

CPC分类号： H01L27/11534 ,  H01L21/823842

摘要： According to one exemplary embodiment, a method for concurrently fabricating a memory region with a logic region in a common substrate includes forming a lower dielectric segment in the common substrate in the memory and logic regions. The method also includes forming a polysilicon segment over the lower dielectric segment in the memory region, while concurrently forming a sacrificial polysilicon segment over the lower dielectric segment in the logic region. Furthermore, the method includes removing from the logic region the lower dielectric segment and the sacrificial polysilicon segment. The method additionally includes forming a high-k segment in the logic region over the common substrate, and in the memory region over the polysilicon segment and forming a metal segment over the high-k segment in the logic and memory regions. An exemplary structure achieved by the described exemplary method is also disclosed.

摘要翻译： 根据一个示例性实施例，用于同时制造具有公共衬底中的逻辑区域的存储区域的方法包括在存储器和逻辑区域中的公共衬底中形成下部介电段。 该方法还包括在存储器区域中的下介电段上形成多晶硅段，同时在逻辑区域中的下介电段上同时形成牺牲多晶硅段。 此外，该方法包括从逻辑区域去除下介电段和牺牲多晶硅段。 该方法还包括在公共衬底上的逻辑区域中形成高k区段，并在多晶硅区段上的存储区域中形成高k区段，并在逻辑和存储区域中的高k区段上形成金属区段。 还公开了通过描述的示例性方法实现的示例性结构。

公开(公告)号：US08748277B2

公开(公告)日：2014-06-10

申请号：US13613520

申请日：2012-09-13

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US08716831B2

公开(公告)日：2014-05-06

申请号：US13249022

申请日：2011-09-29

申请人： Xiangdong Chen ,  Wei Xia

发明人： Xiangdong Chen ,  Wei Xia

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L27/0629 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon substrate with a Shallow Trench Isolation formation, and a process of fabricating same are provided. The eFuse structure enables use of low amounts of current to blow a fuse thus allowing the use of a smaller MOSFET.

摘要翻译： 一种eFuse结构，其具有用作具有栅极的第一金属层，所述栅极包括未经掺杂的多晶硅（poly），第二金属层和高K电介质层，所述第一金属层全部用浅沟槽隔离层形成在硅衬底上，以及工艺 提供制造相同的。 eFuse结构使得能够使用少量的电流来熔断熔丝，从而允许使用更小的MOSFET。

公开(公告)号：US08558300B2

公开(公告)日：2013-10-15

申请号：US12590370

申请日：2009-11-06

申请人： Wei Xia ,  Xiangdong Chen ,  Frank Hui

发明人： Wei Xia ,  Xiangdong Chen ,  Frank Hui

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11526 ,  H01L27/11546

摘要： According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

摘要翻译： 根据一个示例性实施例，一种用于在半导体管芯中制造快闪存储器单元的方法包括：在衬底的存储器区域中形成覆盖浮置栅极堆叠的控制栅极堆叠，其中浮置栅极堆叠包括覆盖一部分 电介质层。 浮栅包括金属一层的一部分，电介质一层包括第一高k电介质材料。 控制栅极堆叠可以包括包括金属两层的一部分的控制栅极，其中金属一层可以包括与金属两层不同的金属。

公开(公告)号：US08445969B2

公开(公告)日：2013-05-21

申请号：US13094873

申请日：2011-04-27

申请人： Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

发明人： Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/7843

摘要： An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.

摘要翻译： 集成电路结构在衬底上包括至少一对互补晶体管。 一对互补晶体管包括第一晶体管和第二晶体管。 此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。 第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。 第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

公开(公告)号：US08441000B2

公开(公告)日：2013-05-14

申请号：US11307331

申请日：2006-02-01

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L29/06

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7391

摘要： The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TPET, the drain region comprises p-doped silicon, while the source region comprises n-doped SiC.

摘要翻译： 本发明涉及异质结隧道效应晶体管（TFET），其包括间隔开的源极和漏极区，其中位于其间的沟道区和位于沟道区上方的栅极叠层。 漏极区域包括第一半导体材料并且掺杂有第一导电类型的第一掺杂物种类。 源区包括第二不同的半导体材料，并且掺杂有第二不同导电类型的第二掺杂物种。 栅极堆叠至少包括栅极电介质和栅极导体。 当异质结TFET是n沟道TFET时，漏极区域包括n掺杂的硅，而源极区域包括p掺杂的硅锗。 当异质结TFET是p沟道TPET时，漏极区包括p掺杂的硅，而源区包括n掺杂的SiC。

公开(公告)号：US20130099317A1

公开(公告)日：2013-04-25

申请号：US13277547

申请日：2011-10-20

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L2029/7857

摘要： According to one exemplary embodiment, a fin-based adjustable resistor includes a fin channel of a first conductivity type, and a gate surrounding the fin channel. The fin-based adjustable resistor also includes first and second terminals of the first conductivity type being contiguous with the fin channel, and being situated on opposite sides of the fin channel. The fin channel is lower doped relative to the first and second terminals. The resistance of the fin channel between the first and second terminals is adjusted by varying a voltage applied to the gate so as to achieve the fin-based adjustable resistor. The gate can be on at least two sides of the fin channel. Upon application of a depletion voltage, the fin channel can be depleted before an inversion is formed in the fin channel.

摘要翻译： 根据一个示例性实施例，鳍状可调电阻器包括第一导电类型的鳍状沟道和围绕鳍状沟道的栅极。 鳍状可调电阻器还包括第一导电类型的第一和第二端子，其与鳍状通道邻接并位于翅片通道的相对侧上。 翅片通道相对于第一和第二端子较低掺杂。 通过改变施加到栅极的电压来调节第一和第二端子之间的鳍状通道的电阻，从而实现基于鳍片的可调电阻器。 门可以在鳍通道的至少两侧。 在施加耗尽电压时，在鳍式通道中形成反转之前，可以耗尽鳍通道。