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公开(公告)号：US20140264540A1
公开(公告)日：2014-09-18
申请号：US14210379
申请日：2014-03-13
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Shyue Seng TAN , Eng Huat TOH
IPC: H01L29/788 , H01L29/66
CPC classification number: H01L27/11524 , H01L27/11521 , H01L27/2436 , H01L29/42328 , H01L29/66825 , H01L29/788 , H01L45/1226 , H01L45/126 , H01L45/1608 , H01L45/1691
Abstract: Devices and methods for forming a device are disclosed. The method includes providing a substrate and forming a memory cell pair on the substrate. Each of a memory cell of the memory cell pair includes at least one transistor having first and second gates formed between first and second terminals and a third gate disposed over the second terminal. The first gate serves as an access gate (AG), the second gate serves as a storage gate and the third gate serves as an erase gate (EG). The first cell terminal serves as a bitline terminal and the second cell terminal serves as a source line terminal. The source line terminal is a raised source line terminal and is elevated with respect to the bit line terminal and the source line terminal is common to the memory cell pair.
Abstract translation: 公开了用于形成装置的装置和方法。 该方法包括提供衬底并在衬底上形成存储单元对。 存储单元对的存储单元中的每一个包括至少一个晶体管，其具有形成在第一和第二端子之间的第一和第二栅极以及设置在第二端子上的第三栅极。 第一栅极用作接入门（AG），第二栅极用作存储栅极，第三栅极用作擦除栅极（EG）。 第一小区终端用作位线终端，第二小区终端用作源线路终端。 源极端子是升高的源极线端子，并且相对于位线端子升高，并且源极线端子对于存储器单元对是共同的。
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公开(公告)号：US20140158970A1
公开(公告)日：2014-06-12
申请号：US14179655
申请日：2014-02-13
Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Inventor： Shyue Seng TAN , Eng Huat TOH , Elgin QUEK
IPC: H01L27/24
CPC classification number: H01L27/2436 , H01L27/2445 , H01L45/08 , H01L45/124 , H01L45/146 , H01L45/1683
Abstract: An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.
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公开(公告)号：US20230083401A1
公开(公告)日：2023-03-16
申请号：US17472722
申请日：2021-09-13
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Guoquan TEO , Meng Yew SEAH , Yongshun SUN , Eng Huat TOH
Abstract: The present disclosure provides a wafer probe card including: a non-magnetic printed circuit board (PCB) having a first side and a second side opposite the first side, the first side configured to face a magnet; a plurality of connection structures provided on the first side of the non-magnetic PCB; and a Hall sensor unit fixedly provided on the first side of the non-magnetic PCB, the Hall sensor electrically connected to at least one of the plurality of connection structures.
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84.发明申请公开(公告)号：US20230076514A1
公开(公告)日：2023-03-09
申请号：US17469221
申请日：2021-09-08
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Vinayak Bharat NAIK , Eng Huat TOH , Kazutaka YAMANE , Hemant M. DIXIT
IPC: G01R33/09
Abstract: The present disclosure relates to integrated circuits, and, more particularly, to a magnetic field sensor using magnetic tunneling junction (MTJ) structures and passive resistors, and methods of manufacture and operation. The structure includes: a first portion of a circuit including a first MTJ structure and a first resistor coupled in series between a first voltage source and a second voltage source; and a second portion of the circuit including a second MTJ structure and a second resistor coupled in series between the first voltage source and the second voltage source. The first portion and the second portion are coupled in parallel between the first voltage source and the second voltage source.
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公开(公告)号：US20220209109A1
公开(公告)日：2022-06-30
申请号：US17136133
申请日：2020-12-29
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Desmond Jia Jun LOY , Eng Huat TOH , Shyue Seng TAN
Abstract: A memory device may be provided, including a first electrode, an insulating element arranged over the first electrode, a second electrode arranged over the insulating element, a switching layer and a conductive line electrically coupled to the second electrode. Each of the first electrode, the insulating element, and the second electrode may include a first side surface and a second side surface. Centers of the first electrode, the insulating element, and the second electrode may be substantially vertically aligned. The first side surface and the second side surface of the second electrode may be substantially vertically aligned with the first side surface and the second side surface of at least one of the insulating element and the first electrode. The switching layer may be conformal to the first side surfaces and the second side surfaces of the second electrode and the insulating element.
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Patent Agency Ranking
公开(公告)号：US20220171001A1
公开(公告)日：2022-06-02
申请号：US17105675
申请日：2020-11-27
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ping ZHENG , Eng Huat TOH , Yongshun SUN
Abstract: A magnetic field sensor may include a semiconductor structure having a planar surface, and first, second, and third sensing devices. The semiconductor structure may include a semiconductor member having a two-dimensional electron gas therein, and an insulator member disposed on the semiconductor member. The first sensing device may be configured to sense magnetic field along a first axis parallel to the planar surface. The second sensing device may be configured to sense magnetic field along a second axis parallel to the planar surface, and orthogonal to the first axis. The third sensing device may be configured to sense a magnetic field along a third axis normal to the planar surface. Each of the first, second, and third sensing devices may be formed in the semiconductor structure and may include electrodes that extend from the insulator member to the two-dimensional electron gas.
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公开(公告)号：US20210286025A1
公开(公告)日：2021-09-16
申请号：US16817623
申请日：2020-03-13
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Yongshun SUN , Eng Huat TOH , Ping ZHENG
Abstract: A Hall effect sensor device may be provided, including one or more sensor structures. Each sensor structure may include: a base layer having a first conductivity type; a Hall plate region having a second conductivity type opposite from the first conductivity type arranged above the base layer; a first isolating region arranged around and adjoining the Hall plate region, and contacting the base layer; a plurality of second isolating regions arranged within the Hall plate region; and a plurality of terminal regions arranged within the Hall plate region. The first and second isolating regions may include electrically insulating material, and each neighboring pair of terminal regions may be electrically isolated from each other by one of the second isolating regions.
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公开(公告)号：US20210247470A1
公开(公告)日：2021-08-12
申请号：US16787226
申请日：2020-02-11
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ping ZHENG , Eng Huat TOH , Kazutaka YAMANE , Shyue Seng TAN , Kiok Boone Elgin QUEK
Abstract: A semiconductor device may be provided including a first series portion and a second series portion electrically connected in parallel with the first series portion. The first series portion may include a first MTJ stack and a first resistive element electrically connected in series. The second series portion may include a second MTJ stack and a second resistive element electrically connected in series. The first resistive element may include a third MTJ stack and the second resistive element may include a fourth MTJ stack. The first, second, third, and fourth MTJ stacks may include a same number of layers, which may include a fixed layer, a free layer, and a tunnelling barrier layer between the fixed layer and the free layer. Alternatively, the first resistive element may include a first transistor and the second resistive element may include a second transistor.
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公开(公告)号：US20200295161A1
公开(公告)日：2020-09-17
申请号：US16886306
申请日：2020-05-28
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Eng Huat TOH , Shyue Seng TAN , Elgin Kiok Boone QUEK
IPC: H01L29/66 , H01L29/78 , H01L27/112 , H01L27/088 , H01L27/12 , H01L29/06 , H01L27/115 , H01L21/84
Abstract: Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.
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公开(公告)号：US20200182826A1
公开(公告)日：2020-06-11
申请号：US16215688
申请日：2018-12-11
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Bin LIU , Eng Huat TOH , Shyue Seng TAN , Ming Tsang TSAI , Khee Yong LIM , Kiok Boone Elgin QUEK
IPC: G01N27/414
Abstract: A sensor device may include a substrate, first and second source regions, first and second drain regions, first and second channel regions, and first and second gate structures disposed over the first and second channel regions, respectively. The source regions and drain regions may be at least partially disposed within the substrate. The first and second source regions may have first and second source resistances, respectively, and the second source resistance may be higher than the first source resistance. The first gate structure may receive a solution, and a change in pH in the solution may cause a change in a first current flow through the first channel region. In turn, the second current flow through the second channel region may change to compensate for the change in the first current flow to maintain a constant current flow through the sensor device.
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