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公开(公告)号：US08239715B2
公开(公告)日：2012-08-07
申请号：US12144686
申请日：2008-06-24
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G11C7/02 , G11C7/04 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C29/1201 , G11C29/12015 , G11C29/48 , G11C2029/5602 , G11C2207/104
摘要： A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins.
摘要翻译： 提供一种用于操作第一单元和提供其数据的第二单元之间的接口的方法。 该方法包括在LSSD_B和LSSD_C时钟之间的切换控制和系统时钟（CLK），以提供测试操作模式和功能操作模式，以根据单元运行的条件来优化建立和保持时间。 在测试模式下，数据由LSSD_C时钟启动。 在功能模式下，数据由系统时钟（CLK）发送到RAM。 还提供了一种方法来确定哪些存储器输入应该使用提供足够的建立和保持余量的电路。
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82.发明授权Circuit and method for asynchronous pipeline processing with variable request signal delay 有权具有可变请求信号延迟的异步流水线处理的电路和方法公开(公告)号：US08188765B2
公开(公告)日：2012-05-29
申请号：US12882425
申请日：2010-09-15
IPC分类号： H03K19/00 , H03K19/096 , H03K19/094 , H03K19/20
CPC分类号： G06F5/10 , G06F2205/104
摘要： Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design.
摘要翻译： 公开了异步管线电路的实施例。 在电路的每个阶段，可变延迟线被并入到请求信号路径中。 抽头编码器监视进入阶段的数据，以检测在特定数据位中发生的任何状态变化。 基于该监视的结果（即，基于特定数据位中的哪一个，如果有的话，表现出状态改变），则分接编码器在可变延迟线中启用特定抽头，从而自动调整请求的延迟 信号沿请求信号路径传输。 使用可变请求信号延迟允许在与发送级相关联的最大可能处理时间到期之前由接收级捕获来自发送级的数据，从而最小化整个处理时间。 还公开了用于具有可变请求信号延迟的异步流水线处理的方法的实施例，并且将可变请求信号延迟并入到异步管线电路设计中。
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公开(公告)号：US07908534B2
公开(公告)日：2011-03-15
申请号：US12036320
申请日：2008-02-25
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318536
摘要： A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L1/L2 master-slave SRL type latch pairs; connects all the system ports of the L1 latches to the Shift Register Input (SRI) and clocked by the system C1-clk while the L1 scan port is clocked by the A-clk and L2 scan port is clocked only by the B-clk. The L1 latches are connected to at least one multiplexer having a first output connected to an input of each odd SRL, and a second output connected to an input port of each even SRL. In another embodiment, the GPTR includes a plurality of multiplexers respectively coupled to the master-slave latch pairs, wherein a first set of multiplexers have their respective output attached to an input of the odd L1 latches, and a second set of the multiplexers have their respective output attached to an input port of the even L1 latches.
摘要翻译： 用于诊断长不可扫描寄存器链（GPTR）的断层扫描链缺陷的结构设计 - 用于测试和诊断断裂的LSSD扫描链的系统快速将缺陷定位到故障移位寄存器锁存器（SRL） ）对。 GPTR将GPTR扫描链中使用的锁存器修改为标准LSSD L1 / L2主从SL型锁存器对; 将L1锁存器的所有系统端口连接到移位寄存器输入（SRI）并由系统C1-clk计时，而L1扫描端口由A-clk计时，L2扫描端口由B-clk提供时钟。 L1锁存器连接到至少一个多路复用器，其具有连接到每个奇数SRL的输入的第一输出，以及连接到每个偶数SRL的输入端口的第二输出。 在另一个实施例中，GPTR包括分别耦合到主从锁存器对的多个复用器，其中第一组复用器具有附加到奇数L1锁存器的输入的相应输出，并且第二组复用器具有它们 相应的输出附加到偶数L1锁存器的输入端口。
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公开(公告)号：US20110029827A1
公开(公告)日：2011-02-03
申请号：US12511739
申请日：2009-07-29
CPC分类号： G11C29/14
摘要： In one embodiment, the invention is a method, apparatus, and design structure for built-in self-test for embedded memory in integrated circuit chips. One embodiment of a method for built-in self-test of an embedded memory includes setting up a plurality of test patterns at a speed of a test clock, where the speed of the test clock is slow enough for a tester to directly communicate with a chip in which the memory is embedded, and where the setting up includes loading a plurality of signal states used to communicate the test patterns to one or more components of a built-in self-test system, applying the test patterns to the embedded memory as a microburst at-speed, capturing output data from the embedded memory at-speed, the output data corresponding to only one of test patterns, and comparing the output data to expected data at the speed of the test clock.
摘要翻译： 在一个实施例中，本发明是用于集成电路芯片中的嵌入式存储器的内置自检的方法，装置和设计结构。 用于嵌入式存储器的内置自检的方法的一个实施例包括以测试时钟的速度设置多个测试图案，其中测试时钟的速度足够慢以使测试者直接与一个 芯片，其中嵌入存储器，并且其中的设置包括将用于将测试图案传送到内置自检系统的一个或多个组件的多个信号状态，将测试图案作为 高速微冲速，以速度从嵌入式存储器捕获输出数据，输出数据仅对应于测试模式之一，并且以测试时钟的速度将输出数据与期望数据进行比较。
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85.发明授权Automatic shutdown or throttling of a BIST state machine using thermal feedback 失效使用热反馈自动关闭或调节BIST状态机公开(公告)号：US07689887B2
公开(公告)日：2010-03-30
申请号：US11962781
申请日：2007-12-21
CPC分类号： G11C29/14 , G01K3/005 , G11C29/12 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译： 内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关联的BIST测试操作，以及包括BIST的设计结构 提供了体现在机器可读介质中的状态机。 热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。 响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。 这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。
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公开(公告)号：US20090319841A1
公开(公告)日：2009-12-24
申请号：US12144703
申请日：2008-06-24
IPC分类号： G06F11/267 , G01R31/28 , G01R31/317
CPC分类号： G11C29/36 , G11C29/1201 , G11C29/48 , G11C2029/0401
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括耦合到数据处理单元输入的输入寄存器和测试操作模式和功能操作模式。 在测试模式操作中，寄存器以时钟模式操作，使得在测试操作模式期间，寄存器响应于时钟信号将数据传播到数据处理单元。 在功能操作模式中，寄存器以数据刷新模式运行，使得寄存器响应于该数据将数据传播到数据处理单元。 功能模式由刷新使能信号使能，测试模式通过刷新使能信号的相反状态使能。
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87.发明申请INTEGRATED CIRCUIT CONTAINING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK 有权包含多状态恢复电路的集成电路，用于将状态恢复到功率管理的功能块公开(公告)号：US20090302889A1
公开(公告)日：2009-12-10
申请号：US12135249
申请日：2008-06-09
IPC分类号： H03K19/0175
CPC分类号： H03K19/0008 , H03K19/173
摘要： Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector.
摘要翻译： 多功能恢复电路，允许在功能块被重新加电时加载功率管理功能块的存储元件，使得功能块在功能块的电压升高之后实际上准备好运行。 多状态恢复电路包括恢复状态检测器，用于确定功能块的多个恢复状态中的哪一个可应用于功能块的特定重新启动。 多状态恢复电路还包括根据由恢复状态检测器确定的恢复状态来加载存储元件的恢复逻辑。
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88.发明申请AUTOMATICALLY EXTENSIBLE ADDRESSING FOR SHARED ARRAY BUILT-IN SELF-TEST (ABIST) CIRCUITRY 有权自动进行自动测试（ABIST）电路的自动寻址公开(公告)号：US20090249146A1
公开(公告)日：2009-10-01
申请号：US12055595
申请日：2008-03-26
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3187 , G01R31/31722
摘要： A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree.
摘要翻译： 一种用于通过自动扩展用于共享阵列内置自检（BIST）电路的寻址来测试集成电路（IC）的方法，包括轮询多个存储器以确定多个存储器中的哪个存储器共享第一比较树并映射 使用第一比较树将共享阵列BIST地址空间分配给多个存储器中的每一个。 另外，该方法包括估计与被测试的最大总存储器地址大小的最高有效位相对应的共享阵列BIST完成时间，重新配置共享阵列BIST电路以适应估计的共享阵列BIST完成时间并测试多个存储器共享 第一个比较树。
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89.发明申请公开(公告)号：US20090161722A1
公开(公告)日：2009-06-25
申请号：US11962781
申请日：2007-12-21
IPC分类号： G01K13/00
CPC分类号： G11C29/14 , G01K3/005 , G11C29/12 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译： 内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关联的BIST测试操作，以及包括BIST的设计结构 提供了体现在机器可读介质中的状态机。 热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。 响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。 这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。
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公开(公告)号：US07478301B2
公开(公告)日：2009-01-13
申请号：US12114198
申请日：2008-05-02
申请人： Leonard O. Farnsworth, III , Michael Z. Felske , Pamela S. Gillis , Benjamin P. Lynch , Michael R. Ouellette , Thomas St. Pierre , Tad J. Wilder , Carl F. Barnhart
发明人： Leonard O. Farnsworth, III , Michael Z. Felske , Pamela S. Gillis , Benjamin P. Lynch , Michael R. Ouellette , Thomas St. Pierre , Tad J. Wilder , Carl F. Barnhart
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318505 , G01R31/318516 , G11C2029/1208 , G11C2029/3202
摘要： An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.
摘要翻译： 集成电路的测试和维修的集成电路和方法。 集成电路包括：具有相同功能的多个宏电路; 保险丝库，保险丝的状态存储测试数据，至少指示哪些宏观电路未通过测试; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏 具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的熔丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。
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