中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

136 records (took 0.023 seconds)

    High density interconnect structures configured for manufacturing and performance
    86.
    发明授权
    High density interconnect structures configured for manufacturing and performance 有权

    公开(公告)号：US11387188B2

    公开(公告)日：2022-07-12

    申请号：US17091657

    申请日：2020-11-06

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

    IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/31

    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

    Microelectronic assemblies
    87.
    发明授权
    Microelectronic assemblies 有权

    公开(公告)号：US11348897B2

    公开(公告)日：2022-05-31

    申请号：US16647863

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Adel A. Elsherbini ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Johanna M. Swan ,  Patrick Morrow ,  Kimin Jun ,  Brennen Mueller ,  Paul B. Fischer

    IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

    Substrate integrated inductors using high throughput additive deposition of hybrid magnetic materials
    88.
    发明授权
    Substrate integrated inductors using high throughput additive deposition of hybrid magnetic materials 有权

    公开(公告)号：US11282800B2

    公开(公告)日：2022-03-22

    申请号：US16651939

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Feras Eid ,  Georgios C. Dogiamis

    IPC: H01L23/64 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

    Abstract: An inductor in a device package and a method of forming the inductor in the device package are described. The inductor includes a first conductive layer disposed on a substrate. The inductor also has one or more hybrid magnetic additively manufactured (HMAM) layers disposed over and around the first conductive layer to form one or more via openings over the first conductive layer. The inductor further includes one or more vias disposed into the one or more via openings, wherein the one or more vias are only disposed on the portions of the exposed first conductive layer. The inductor has a dielectric layer disposed over and around the one or more vias, the HMAM layers, and the substrate. The inductor also has a second conductive layer disposed over the one or more vias and the dielectric layer.

Patent Agency Ranking