公开(公告)号：US20180077270A1

公开(公告)日：2018-03-15

申请号：US15260613

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Daniel Rivas Barragan

IPC: H04L29/08 ,  H04L12/50 ,  H04L1/16

CPC classification number: H04L69/324 ,  G06F15/173 ,  H04L1/1642 ,  H04L12/50 ,  H04L49/00

Abstract: Technologies for using fabric supported sequencers in fabric architectures includes a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to receive an sequencer access message from one of the plurality of computing nodes that includes an identifier of a sequencing counter corresponding to a sequencer session and one or more operation parameters. The network switch is additionally configured to perform an operation on a value associated with the identifier of the sequencing counter as a function of the one or more operation parameters, increment the identifier of the sequencing counter, and associate a result of the operation with the incremented identifier of the sequencing counter. The network switch is further configured to transmit an acknowledgment of successful access to the computing node that includes the result of the operation and the incremented identifier of the sequencing counter. Other embodiments are described herein.

公开(公告)号：US20170344283A1

公开(公告)日：2017-11-30

申请号：US15167953

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Alejandro Duran Gonzalez ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G06F12/0284 ,  G06F2212/2542

Abstract: Technology for an apparatus is described. The apparatus can receive a command to copy data. The command can indicate a first address, a second address and an offset value. The apparatus can determine a first non-uniform memory access (NUMA) domain ID for the first address and a second NUMA domain ID for the second address. The apparatus can identify a first computing node with memory that corresponds to the first NUMA domain ID and a second computing node with memory that corresponds to the second NUMA domain ID. The apparatus can generate an instruction for copying data in a first memory range of the first computing node to a second memory range of the second computing node. The first memory range can be defined by the first address and the offset value and the second memory range can be defined by the second address and the offset value.

公开(公告)号：US09547594B2

公开(公告)日：2017-01-17

申请号：US13843760

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Thomas Willhalm

IPC: G06F12/0811 ,  G06F12/08 ,  G06F9/46

CPC classification number: G06F12/0804 ,  G06F9/467 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F2212/202 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/621

Abstract: A processor in described having an interface to non-volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified by a transaction which views the non-volatile random access memory as the transaction's persistence storage. The logic circuitry is also to identify cache lines modified by a software process other than a transaction that also views said non-volatile random access memory as persistence storage.

Abstract translation: 所描述的处理器具有与非易失性随机存取存储器和逻辑电路的接口。 逻辑电路是识别由事务修改的高速缓存线，其将非易失性随机存取存储器视为事务的持久性存储。 逻辑电路还用于识别除了将所述非易失性随机存取存储器视为持续存储的事务之外的软件过程修改的高速缓存行。

公开(公告)号：US20140223140A1

公开(公告)日：2014-08-07

申请号：US13994505

申请日：2011-12-23

Applicant: INTEL CORPORATION

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Thomas Willhalm

IPC: G06F9/30

CPC classification number: G06F9/30018 ,  G06F9/30036 ,  G06F9/30149 ,  G06F9/3867

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed unary encoding using masks in response to a single vector packed unary encoding using masks instruction that includes a source vector register operand, a destination writemask register operand, and an opcode are described.

Abstract translation: 用于在计算机处理器中执行向量压缩的一元编码的系统，装置和方法在使用掩模的响应于使用包括源向量寄存器操作数，目的地写入寄存器操作数和操作码的掩码指令的单向量压缩一元编码的情况下， 描述。

公开(公告)号：US20240385884A1

公开(公告)日：2024-11-21

申请号：US18571092

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Timothy Verrall ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Zhongyan Lu

IPC: G06F9/50

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to estimate workload complexity. An example apparatus includes processor circuitry to perform at least one of first, second, or third operations to instantiate payload interface circuitry to extract workload objective information and service level agreement (SLA) criteria corresponding to a workload, and acceleration circuitry to select a pre-processing model based on (a) the workload objective information and (b) feedback corresponding to workload performance metrics of at least one prior workload execution iteration, execute the pre-processing model to calculate a complexity metric corresponding to the workload, and select candidate resources based on the complexity metric.

公开(公告)号：US11994932B2

公开(公告)日：2024-05-28

申请号：US16907264

申请日：2020-06-21

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Thomas Willhalm ,  Francesc Guim Bernat

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287

CPC classification number: G06F1/3275 ,  G06F1/3287

Abstract: Methods and apparatus for platform ambient data management schemes for tiered architectures. A platform including one or more CPUs coupled to multiple tiers of memory comprising various types of DIMMs (e.g., DRAM, hybrid, DCPMM) is powered by a battery subsystem receiving input energy harvested from one or more green energy sources. Energy threshold conditions are detected, and associated memory reconfiguration is performed. The memory reconfiguration may include but is not limited to copying data between DIMMs (or memory ranks on the DIMMS in the same tier, copying data between a first type of memory to a second type of memory on a hybrid DIMM, and flushing dirty lines in a DIMM in a first memory tier being used as a cache for a second memory tier. Following data copy and flushing operations, the DIMMs and/or their memory devices are powered down and/or deactivated. In one aspect, machine learning models trained on historical data are employed to project harvested energy levels that are used in detecting energy threshold conditions.

公开(公告)号：US11907136B2

公开(公告)日：2024-02-20

申请号：US16820630

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Ginger H. Gilsdorf ,  Karthik Kumar ,  Mark A. Schmisseur ,  Thomas Willhalm ,  Francesc Guim Bernat

IPC: G06F12/123 ,  G06F12/0891 ,  G11C7/22 ,  G06F1/14 ,  G06F12/02

CPC classification number: G06F12/123 ,  G06F1/14 ,  G06F12/0246 ,  G06F12/0891 ,  G11C7/22

Abstract: An apparatus and/or system is described including a memory device including a memory range and a temporal data management unit (TDMU) coupled to the memory device to receive from an interface, the memory range and a temporal range corresponding to validity of data in the memory range, check the temporal range against a time and/or date value provided by a timer or clock to identify the data in the memory range as expired, and invalidate the data that is expired in the memory device. In some embodiments, the TDMU includes hardware logic that resides on a memory module with the memory device and is coupled to invalidate expired data when the memory module is decoupled from the interface. Other embodiments may be disclosed and claimed.

公开(公告)号：US20220200788A1

公开(公告)日：2022-06-23

申请号：US17561558

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Timothy Verrall ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Ned M. Smith ,  Rajesh Poornachandran ,  Kapil Sood ,  Tarun Viswanathan ,  John J. Browne ,  Patrick Kutch

IPC: H04L9/08

Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.

公开(公告)号：US11366588B2

公开(公告)日：2022-06-21

申请号：US15640943

申请日：2017-07-03

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Nicolae O. Popovici ,  Charles A. Giefer ,  Gaspar Mora Porta ,  Thomas Willhalm

IPC: G06F3/06 ,  H04L69/22 ,  H04L67/1097 ,  H04L67/61

Abstract: A fabric interface apparatus, including: a fabric interface logic to communicatively couple to a fabric; a data interface to communicatively couple to a compute platform including memory resources in at least two memory tiers; and a tier-aware read/write engine (TARWE) to: receive an incoming packet via the fabric; parse a header of the incoming packet to identify a hint for directing the incoming packet to a preferred memory tier; and write the incoming packet to the preferred memory tier.

公开(公告)号：US20220166847A1

公开(公告)日：2022-05-26

申请号：US17542175

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Petar Torre ,  Ned Smith ,  Brinda Ganesh ,  Evan Custodio ,  Suraj Prabhakaran

IPC: H04L67/60 ,  H04L12/66 ,  H04L47/70 ,  H04L67/2885 ,  H04L67/5681

Abstract: Technologies for fulfilling service requests in an edge architecture include an edge gateway device to receive a request from an edge device or an intermediate tier device of an edge network to perform a function of a service by an entity hosting the service. The edge gateway device is to identify one or more input data to fulfill the request by the service and request the one or more input data from an edge resource identified to provide the input data. The edge gateway device is to provide the input data to the entity associated with the request.