公开(公告)号：US20230090521A1

公开(公告)日：2023-03-23

申请号：US17479623

申请日：2021-09-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Carl Radens ,  Lawrence A. Clevenger ,  Daniel James Dechene ,  Hsueh-Chung Chen

IPC: G06F21/16

Abstract: Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.

公开(公告)号：US20220416157A1

公开(公告)日：2022-12-29

申请号：US17449515

申请日：2021-09-30

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Carl Radens ,  Juntao Li ,  Ruilong Xie ,  Praneet Adusumilli ,  Oscar van der Straten ,  Alexander Reznicek ,  Zuoguang Liu ,  Arthur Gasasira

IPC: H01L45/00

Abstract: A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.

公开(公告)号：US20220302377A1

公开(公告)日：2022-09-22

申请号：US17207798

申请日：2021-03-22

Applicant: International Business Machines Corporation

Inventor： JUNTAO LI ,  Kangguo Cheng ,  Carl Radens ,  Ruilong Xie

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor structure for a vertical phase change memory cell that includes a bottom electrode on a portion of a semiconductor substrate and a pair of vertical phase change bridge elements that are each on a portion of the bottom electrode. The semiconductor structure for the vertical phase change memory cell includes a dielectric material separating the pair of vertical phase change bridge elements and a top electrode over the pair of vertical phase change bridge elements.

公开(公告)号：US11349001B2

公开(公告)日：2022-05-31

申请号：US16598065

申请日：2019-10-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Carl Radens ,  Kangguo Cheng ,  Veeraraghavan Basker ,  Juntao Li

IPC: H01L21/8238 ,  H01L27/11 ,  H01L29/417 ,  H01L27/092 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A method of fabricating a static random-access memory (SRAM) device includes forming a sacrificial material and replacing the sacrificial material with a metal to form a cross-couple contact on a metal gate stack. A portion of the metal gate stack directly contacts each of a sidewall and an endwall of the cross-couple contact.

公开(公告)号：US11322402B2

公开(公告)日：2022-05-03

申请号：US16540497

申请日：2019-08-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chih-Chao Yang ,  Carl Radens ,  Juntao Li ,  Kangguo Cheng

IPC: H01L21/768 ,  H01L23/522

Abstract: A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via.

公开(公告)号：US11152307B2

公开(公告)日：2021-10-19

申请号：US16223832

申请日：2018-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Carl Radens ,  Junli Wang ,  John H. Zhang

IPC: H01L23/535 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/11

Abstract: A semiconductor structure includes a plurality of field effect transistors formed on a substrate including p-type doped field effect transistors (pFETs) and n-type doped field effect transistors (nFETs). A self-aligned buried local interconnect electrically connects a bottom source or drain region of the pFET with an adjacent bottom source or drain region of the nFET. The self-aligned buried local interconnect is serially aligned with and intermediate opposing ends of a gate electrode. Other embodiments include methods for forming the buried local interconnect.

公开(公告)号：US11107731B1

公开(公告)日：2021-08-31

申请号：US16834725

申请日：2020-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chih-Chao Yang ,  Carl Radens ,  Juntao Li ,  Kangguo Cheng

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522

Abstract: A method for fabricating a semiconductor device includes forming conductive material on a first metallization level including at least one via disposed on at least one conductive line, subtractively patterning the conductive material to form at least one conductive layer corresponding to at least one conductive line of a second metallization level misaligned with the at least one via of the first metallization level, and at least one cavity within the at least one via forming at least one damaged via resulting from the misalignment, and filling the at least one cavity with conductive liner material to form a filled cavity to repair the at least one damaged via.

公开(公告)号：US20210265166A1

公开(公告)日：2021-08-26

申请号：US16795718

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel James Dechene ,  Somnath Ghosh ,  Hsueh-Chung Chen ,  Carl Radens ,  Lawrence A. Clevenger

IPC: H01L21/033

Abstract: A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

公开(公告)号：US11081172B1

公开(公告)日：2021-08-03

申请号：US16838157

申请日：2020-04-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Carl Radens ,  Ruilong Xie ,  Juntao Li

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/56 ,  G06F21/71

Abstract: A method is presented for forming an on-chip security key. The method includes electrically connecting a pair of phase change memory (PCM) elements in series, electrically connecting a programming transistor to the pair of PCM elements, electrically connecting an input of an inverter to a common node of the pair of PCM elements, setting the PCM elements to a low resistance state (LRS) in an initialization stage, applying a RESET pulse to generate a security bit and to cause one of the PCM elements to change to a high resistance state (HRS), and generating a logic “1” or “0” at the output of the inverter.

公开(公告)号：US10985063B2

公开(公告)日：2021-04-20

申请号：US16542595

申请日：2019-08-16

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Lawrence A. Clevenger ,  Carl Radens ,  Junli Wang ,  John H. Zhang

IPC: H01L21/70 ,  H01L21/768 ,  H01L27/092 ,  H01L21/8238

Abstract: A first TS is coupled to first S/D over first fin, second TS coupled to second S/D over first fin, third TS coupled to third S/D over second fin, fourth TS coupled to fourth S/D over second fin, gate metal over first and second fins, and gate cap over gate metal. First TS cap is on first TS, second TS cap on second TS, third TS cap on third TS, and fourth TS cap on fourth TS. ILD is formed on top of gate cap and first through fourth TS caps. First opening is through ILD and second TS cap such that part of gate metal is exposed, after removing part of gate cap. Second opening is through ILD to expose another part of gate metal. Combined gate metal contact and local metal connection is formed in first opening and individual gate metal contact is formed in second opening.