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    NANOSHEET TRANSISTOR WITH ROBUST SOURCE/DRAIN ISOLATION FROM SUBSTRATE
    1.
    发明申请
    NANOSHEET TRANSISTOR WITH ROBUST SOURCE/DRAIN ISOLATION FROM SUBSTRATE 审中-公开

    公开(公告)号：US20200006476A1

    公开(公告)日：2020-01-02

    申请号：US16545867

    申请日：2019-08-20

    申请人： International Business Machines Corporation

    发明人： Robin Hsin Kuo Chao ,  Kangguo Cheng ,  Cheng Chi ,  Ruilong Xie ,  John H. Zhang

    IPC分类号： H01L29/06 ,  H01L29/775 ,  H01L29/66

    摘要： A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.

    Technique for fabrication of microelectronic capacitors and resistors
    9.
    发明授权
    Technique for fabrication of microelectronic capacitors and resistors 有权
    微电子电容器和电阻器制造技术

    公开(公告)号：US09385177B2

    公开(公告)日：2016-07-05

    申请号：US14068198

    申请日：2013-10-31

    申请人： STMicroelectronics, Inc. ,  International Business Machines Corporation

    发明人： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

    IPC分类号： H01L49/02 ,  H01L23/525 ,  H01L27/01 ,  H01L21/3105 ,  H01L23/522 ,  H01L21/321

    CPC分类号： H01L27/016 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5252 ,  H01L23/5256 ,  H01L28/20 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

    摘要翻译： 半导体处理步骤的顺序允许在公共结构内形成垂直和水平的纳米级蛇形电阻器和平行板电容器。 制造这种结构的方法巧妙地利用CMP工艺不均匀性，其中绝缘材料的CMP抛光速率根据某些基础形貌而变化。 通过在绝缘材料层之下建立这样的形貌，可以通过利用差分抛光速率在不同的区域产生绝缘体的不同膜厚度，从而避免使用光刻掩模。 在一个实施例中，使用仅需要两个掩模层的工艺，可以在公共介电块内形成多个电阻器和电容器作为紧凑的集成结构。 这样形成为一组集成电路元件的电阻器和电容器分别适合用作微电子熔丝和反熔丝，以保护下面的微电子电路。

    INTERCONNECT STRUCTURE HAVING LARGE SELF-ALIGNED VIAS
    10.
    发明申请
    INTERCONNECT STRUCTURE HAVING LARGE SELF-ALIGNED VIAS 有权
    具有大型自对准VIAS的互连结构

    公开(公告)号：US20150279784A1

    公开(公告)日：2015-10-01

    申请号：US14231448

    申请日：2014-03-31

    申请人： International Business Machines Corporation ,  STMicroelectronics, Inc.

    发明人： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Terry Spooner ,  Nicole A. Saulnier

    IPC分类号： H01L23/532 ,  G03F1/36 ,  H01L21/768

    CPC分类号： G03F1/36 ,  G03F1/00 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

    摘要翻译： 公开了一种容纳小金属线和大通孔的波浪线互连结构。 用于图形金属线沟槽的光刻掩模设计使用光学邻近校正（OPC）技术来使用矩形不透明特征来近似波浪线。 可以使用自对准双镶嵌工艺形成大通孔，而不需要单独的通孔光刻掩模。 相反，牺牲层允许蚀刻下面的厚介质块，同时保护对应于金属线互连的沟槽的窄特征。 所得到的通孔具有相对容易填充的纵横比，而较大的通孔覆盖区提供低通孔电阻。 通过提升通孔的收缩约束，从而允许通孔覆盖区超过金属线宽度的最小尺寸，为另外的工艺世代清除了一条路径，以继续将金属线收缩到低于10nm的尺寸。