公开(公告)号：US08871107B2

公开(公告)日：2014-10-28

申请号：US13838763

申请日：2013-03-15

Applicant: International Business Machines Corporation ,  Applied Materials, Inc.

Inventor： Nicholas C. M. Fuller ,  Eric A. Joseph ,  Hiroyuki Miyazoe ,  Mark Hoinkis ,  Chun Yan

IPC: C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  C23F3/00 ,  H01L21/44 ,  H01L21/302 ,  H01L21/461 ,  H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76852

Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.

Abstract translation: 提供了一种在集成电路中形成至少一种金属或金属合金特征的方法。 在一个实施例中，该方法包括提供材料堆叠，其至少包括位于金属或金属合金的擦除层上的蚀刻掩模。 使用不含蚀刻掩模保护的金属或金属合金的覆盖层的暴露部分使用包含等离子体的蚀刻来去除，所述等离子体形成聚合物和/或复合物，所述复合物和/或复合物保护位于金属或金属合金的橡皮布层的一部分 在蚀刻期间直接在蚀刻掩模下面。

公开(公告)号：US20140273437A1

公开(公告)日：2014-09-18

申请号：US13838763

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  APPLIED MATERIALS, INC.

Inventor： Nicholas C. M. Fuller ,  Eric A. Joseph ,  Hiroyuki Miyazoe ,  Mark Hoinkis ,  Chun Yan

IPC: H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76852

Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.

Abstract translation: 提供了一种在集成电路中形成至少一种金属或金属合金特征的方法。 在一个实施例中，该方法包括提供材料堆叠，其至少包括位于金属或金属合金的擦除层上的蚀刻掩模。 使用不含蚀刻掩模保护的金属或金属合金的覆盖层的暴露部分使用包含等离子体的蚀刻来去除，所述等离子体形成聚合物和/或复合物，所述复合物和/或复合物保护位于金属或金属合金的橡皮布层的一部分 在蚀刻期间直接在蚀刻掩模下面。

公开(公告)号：US20140264861A1

公开(公告)日：2014-09-18

申请号：US13836739

申请日：2013-03-15

Applicant: Applied Materials, Incorporated ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： MARK D. HOINKIS ,  Eric A. Joseph ,  Hiroyuki Miyazoe ,  Chun Yan

IPC: H01L21/3213

CPC classification number: H01L21/32136 ,  H01L21/32139 ,  H01L21/76852 ,  H01L21/76885

Abstract: A method for fabricating one or more conductive lines in an integrated circuit includes providing a layer of copper containing conductive metal in a multi-layer structure fabricated upon a wafer, providing a first hard mask layer over the layer of copper containing conductive metal, performing a first sputter etch of first hard mask layer using a chlorine-based plasma or a sulfur fluoride-based plasma, and performing a second sputter etch of first hard mask layer using a second plasma, wherein a portion of the layer of copper containing conductive metal residing below a portion of the first hard mask layer that remains after the second sputter etch forms the one or more conductive lines. In one embodiment, the second plasma is a fluorocarbon-based plasma.

Abstract translation: 一种用于在集成电路中制造一个或多个导电线的方法包括在制造在晶片上的多层结构中提供含铜导电金属层，在含铜导电金属层上提供第一硬掩模层， 使用基于氯的等离子体或基于硫氟化物的等离子体对第一硬掩模层进行第一溅射蚀刻，以及使用第二等离子体进行第一硬掩模层的第二溅射蚀刻，其中所述含铜导电金属层的一部分驻留 在第二溅射蚀刻之后残留的第一硬掩模层的一部分之下形成一个或多个导电线。 在一个实施例中，第二等离子体是基于碳氟化合物的等离子体。

公开(公告)号：US20140252629A1

公开(公告)日：2014-09-11

申请号：US13972178

申请日：2013-08-21

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/48 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided.

Abstract translation: 提供了涉及混合（消减图案/镶嵌）金属化方法的金属布线的自对准间距分割技术。 一方面，在晶片上形成金属配线层的方法包括以下步骤。 在晶片上形成铜层。 在铜层上形成图案化的硬掩模。 使用图案化的硬掩模对铜层进行减法图案化以形成多条第一铜线。 隔板形成在第一铜线的相对侧上。 将平坦化介电材料沉积到晶片上，填充第一铜线之间的空间。 在平坦化介电材料中蚀刻一个或多个沟槽。 沟槽用铜填充以形成与第一铜线自对准的多条第二铜线。 还提供电子设备。

公开(公告)号：US20140191371A1

公开(公告)日：2014-07-10

申请号：US13735314

申请日：2013-01-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric A. Joseph ,  David W. Abraham ,  Roger W. Cheek ,  Alejandro G. Schroit ,  Ying Zhang

IPC: H01L21/306 ,  H01L29/06 ,  H01L21/67

CPC classification number: H01L21/3081 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32134 ,  H01L21/32137 ,  H01L29/0657 ,  H01L29/16 ,  Y10T428/24479 ,  Y10T428/24612

Abstract: A material can be locally etched with arbitrary changes in the direction of the etch. A ferromagnetic-material-including catalytic particle is employed to etch the material. A wet etch chemical or a plasma condition can be employed in conjunction with the ferromagnetic-material-including catalytic particle to etch a material through a catalytic reaction between the catalytic particle and the material. During a catalytic etch process, a magnetic field is applied to the ferromagnetic-material-including catalytic particle to direct the movement of the particle to any direction, which is chosen so as to form a contiguous cavity having at least two cavity portions having different directions. The direction of the magnetic field can be controlled so as to form the contiguous cavity in a preplanned pattern, and each segment of the contiguous cavity can extend along an arbitrary direction.

Abstract translation: 可以在蚀刻方向上任意变化地局部蚀刻材料。 使用含铁磁材料的催化颗粒来蚀刻材料。 湿蚀刻化学品或等离子体条件可以与含铁磁材料的催化颗粒结合使用，以通过催化颗粒和材料之间的催化反应来蚀刻材料。 在催化蚀刻工艺期间，磁场被施加到包含铁磁材料的催化剂颗粒上以引导颗粒运动到任何方向，该方向被选择成形成具有至少两个具有不同方向的空腔部分的连续空腔 。 可以控制磁场的方向以便以预先设计的图案形成连续的空腔，并且连续空腔的每个区段可以沿任意方向延伸。

公开(公告)号：US20140183667A1

公开(公告)日：2014-07-03

申请号：US13733404

申请日：2013-01-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Eric A. Joseph ,  Satyavolu S. Papa Rao

IPC: H01L29/66

CPC classification number: H01L29/66007 ,  B01L3/502707 ,  G01N33/48721 ,  G01N33/54373 ,  H01L29/66

Abstract: A pair of electrode plates can be provided by directional deposition and patterning of a conductive material on sidewalls of a template structure on a first dielectric layer. An electrode line straddling the center portion is formed. A dielectric spacer and a conformal conductive layer are subsequently formed. Peripheral electrodes laterally spaced from the electrode line are formed by pattering the conformal conductive layer. After deposition of a second dielectric material layer that encapsulates the template structure, the template structure is removed to provide a cavity that passes through the pair of electrode plates, the electrode line, and the peripheral electrodes. A nanoscale sensor thus formed can electrically characterize a nanoscale string by passing the nanoscale string through the cavity while electrical measurements are performed employing the various electrodes.

Abstract translation: 可以通过在第一电介质层上的模板结构的侧壁上的导电材料的定向沉积和图案化来提供一对电极板。 形成跨越中心部的电极线。 随后形成电介质间隔物和共形导电层。 通过图案保形导电层形成与电极线横向隔开的外围电极。 在沉积封装模板结构的第二介电材料层之后，去除模板结构以提供穿过一对电极板，电极线和外围电极的空腔。 如此形成的纳米尺度传感器可以通过使纳米尺度的串通过空腔来电性地表征纳米尺度的串，同时使用各种电极执行电测量。

公开(公告)号：US20140159242A1

公开(公告)日：2014-06-12

申请号：US13734524

申请日：2013-01-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cyril Cabral, JR. ,  Sebastian U. Engelmann ,  Benjamin L. Fletcher ,  Michael S. Gordon ,  Eric A. Joseph

IPC: H01L29/45

CPC classification number: H01L23/48 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer pitches, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices and having sub-eighty nanometer line widths, wherein the conductive lines include a transition metal and a protective cap deposited on the transition metal, wherein the protective cap has a thickness between approximately five and fifteen nanometers.

Abstract translation: 集成电路包括多个半导体器件和连接半导体器件的多条导线，其中导线包括沉积在过渡金属上的过渡金属和保护帽。 或者，集成电路包括多个半导体器件和连接半导体器件并具有八十纳米间距的多条导线，其中导电线包括沉积在过渡金属上的过渡金属和保护帽，其中保护性 帽的厚度在约5至15纳米之间。 或者，集成电路包括多个半导体器件和连接半导体器件并具有八十纳米线宽的多条导线，其中导电线包括沉积在过渡金属上的过渡金属和保护帽，其中， 保护帽的厚度介于约5至15纳米之间。

公开(公告)号：US20140124870A1

公开(公告)日：2014-05-08

申请号：US13970678

申请日：2013-08-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cyril Cabral, JR. ,  Benjamin L. Fletcher ,  Nicholas C.M. Fuller ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L27/092

CPC classification number: H01L23/535 ,  H01L21/02109 ,  H01L21/31111 ,  H01L21/32131 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76885 ,  H01L21/823871 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.

Abstract translation: 集成电路的一个实施例包括多个半导体器件和连接多个半导体器件的多条导线，其中多条导线中的至少一些具有小于百纳米的间距，以及约八十 和九十度。 集成电路的另一实施例包括多个半导体器件和连接多个半导体器件的多条导线，其中通过提供多层结构中的导电金属层来制造多条导线中的至少一些 制造在晶片上并使用甲醇等离子体溅射蚀刻导电金属层，其中在溅射蚀刻之后保留的导电金属层的一部分形成一个或多个导电线。