公开(公告)号：US20170373167A1

公开(公告)日：2017-12-28

申请号：US15622769

申请日：2017-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/3083 ,  H01L21/3085 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785

Abstract: Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.

公开(公告)号：US20170373166A1

公开(公告)日：2017-12-28

申请号：US15195332

申请日：2016-06-28

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/3085 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.

公开(公告)号：US09728622B1

公开(公告)日：2017-08-08

申请号：US15149764

申请日：2016-05-09

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/28 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49 ,  H01L21/02

CPC classification number: H01L29/6653 ,  H01L21/28247 ,  H01L29/0657 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66795

Abstract: Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.

公开(公告)号：US20170221708A1

公开(公告)日：2017-08-03

申请号：US15008615

申请日：2016-01-28

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/02603 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.

公开(公告)号：US09362179B1

公开(公告)日：2016-06-07

申请号：US14746223

申请日：2015-06-22

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ryan O. Jung ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/8238 ,  H01L21/322 ,  H01L21/308 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/161

CPC classification number: H01L27/0924 ,  H01L21/3081 ,  H01L21/3221 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a silicon germanium alloy is formed in a pFET device region. A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor. A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin. Functional gate structures can be formed straddling over each of the various fins.

Abstract translation: 在nFET器件区域中形成硅鳍前体，并且在pFET器件区域中形成包括硅的交替材料部分以及从底部到顶部的硅和硅锗合金的鳍片堆叠。 然后使用热退火将翅片叠层转换成硅锗合金翅片前体。 热氧化工艺之后，将硅翅片前体转化成硅翅片，将硅锗合金翅片前体转化成硅锗合金翅片。 功能门结构可跨越各个翅片跨越形成。