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公开(公告)号：US09760374B2
公开(公告)日：2017-09-12
申请号：US13067805
申请日：2011-06-28
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30134 , G06F9/3824
摘要： A data processing system 2 includes a stack pointer register 26, 28, 30, 32 storing a stack pointer value for use in stack access operations to a stack data store 44, 46, 48, 50. Stack alignment checking circuitry 36 which is selectively disabled may be provided to check memory address alignment of the stack pointer value associated with a stack memory access. The action of the stack alignment checking circuitry 36 is independent of any further other alignment checking performed in respect of all memory accesses. Thus, general alignment checking circuitry 38 may be provided and independently selectively disabled in respect of any memory access.
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公开(公告)号：US08959318B2
公开(公告)日：2015-02-17
申请号：US13067808
申请日：2011-06-28
CPC分类号： G06F9/30101 , G06F9/30181 , G06F9/30189 , G06F9/30196 , G06F9/3861
摘要： A data processing system 2 supporting multiple modes of operation is provided with illegal change detecting circuitry 22 which detects attempts by program instructions to perform an illegal change of mode, such as a change to a higher level of privilege in response to execution of a mode changing program instruction or an exception return instruction. If such a change is detected, then an illegal change bit CPSR.IL is set. An instruction decoder 12 is responsive to the illegal change bit having a set value to treat subsequent program instructions as undefined instructions. These undefined instructions may then trigger an undefined instruction exception or other type of response.
摘要翻译： 提供了支持多种操作模式的数据处理系统2，其具有非法变化检测电路22，其检测由程序指令执行模式的非法改变的尝试，例如响应于模式改变的执行而改变为更高级别的特权 程序指令或异常返回指令。 如果检测到这种变化，则设置非法更改位CPSR.IL。 指令解码器12响应于具有设定值的非法变更位以将后续的程序指令视为未定义的指令。 这些未定义的指令可能会触发未定义的指令异常或其他类型的响应。
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公开(公告)号：US08713371B2
公开(公告)日：2014-04-29
申请号：US13296445
申请日：2011-11-15
IPC分类号： G06F11/00
CPC分类号： G06F11/3656 , G06F9/4812
摘要： A data processing apparatus for performing data processing operations in response to execution of program instructions and debug circuitry for performing operations. The data processing apparatus includes a data store for storing a current debug exception mask value. The data processing circuitry is configured to set the mask value to a first value in the data store in response to executing critical code and on termination of execution of the critical code to reset the mask value to not store the first value. The data processing circuitry is configured, in response to receipt of a control signal indicating a debug exception is to be taken, to allow the exception to be taken if the mask value is not set to the first value and not to allow said exception to be taken if the mask value is set to the first value.
摘要翻译： 一种用于响应于程序指令的执行和用于执行操作的调试电路执行数据处理操作的数据处理装置。 数据处理装置包括用于存储当前调试异常掩码值的数据存储器。 数据处理电路被配置为响应于执行关键代码并且终止关键代码的执行而将掩码值设置在数据存储器中的第一值以重置掩码值以不存储第一值。 数据处理电路被配置为响应于接收到指示调试异常的控制信号，以允许在掩码值未被设置为第一值而不允许所述异常为 如果掩码值被设置为第一个值则采取。
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公开(公告)号：US20140052921A1
公开(公告)日：2014-02-20
申请号：US14113723
申请日：2012-05-21
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F9/3004 , G06F9/3834 , G06F12/0815 , G06F12/0817
摘要： A data processing system includes a plurality of transaction masters (4, 6, 8, 10) each with an associated local cache memory (12, 14, 16, 18) and coupled to coherent interconnect circuitry (20). Monitoring circuitry (24) within the coherent interconnect circuitry (20) maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.
摘要翻译： 数据处理系统包括多个具有相关本地高速缓存存储器（12,14,16,18）并且耦合到相干互连电路（20）的交易主机（4,6,8,10）。 相干互连电路（20）内的监控电路（24）维护关于每个交易主机的状态变量（标志），以监视该交易主机的独占存储访问状态是否正在等待。 当事务主机要执行存储专用指令时，将该事务主机的主体状态变量的当前值与设置独占存储访问时存储的该变量的先前值进行比较。 如果存在匹配，则允许存储专用指令继续进行，并且具有挂起的独占存储访问状态的所有其他事务主器件的状态变量被改变。 如果没有匹配，则专用指令的执行被标记为失败。
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公开(公告)号：US08566563B2
公开(公告)日：2013-10-22
申请号：US13064243
申请日：2011-03-14
CPC分类号： G06F12/10 , G06F12/1009 , G06F2212/651
摘要： Memory address translation circuitry 14 performs a top down page table walk operation to translate a virtual memory address VA to a physical memory address PA using translation data stored in a hierarchy of translation tables 28, 32, 36, 38, 40, 42. A page size variable S is used to control the memory address translation circuitry 14 to operate with different sizes S of pages of physical memory addresses, pages of virtual memory address and translation tables. These different sizes may be all 4 kBs or all 64 kBs. The system may support multiple virtual machine execution environments. These virtual machine execution environments can independently set their own page size variable as can the page size of an associated hypervisor 62.
摘要翻译： 存储器地址转换电路14执行自顶向下的页面行进操作，以使用存储在转换表28,32,36,38,40,40的层级中的转换数据将虚拟存储器地址VA转换为物理存储器地址PA。页面 大小变量S用于控制存储器地址转换电路14以不同尺寸的物理存储器地址页面，虚拟存储器地址和转换表的页面进行操作。 这些不同的大小可以是所有4 kB或全部64 kB。 该系统可以支持多个虚拟机执行环境。 这些虚拟机执行环境可以独立地设置自己的页面大小变量，以及相关联的管理程序62的页面大小。
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公开(公告)号：US08375170B2
公开(公告)日：2013-02-12
申请号：US12656709
申请日：2010-02-12
申请人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Andrew Christopher Rose , Richard Roy Grisenthwaite
发明人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Andrew Christopher Rose , Richard Roy Grisenthwaite
CPC分类号： G06F12/0815 , G06F2212/507 , Y02D10/13
摘要： A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache. Such a mechanism causes the refetch of data into the cache to be triggered by the coherency action performed in response to a coherency request from another portion of the coherent cache system, rather than relying on any actions taken by the at least one master device, thereby providing a very flexible and efficient mechanism for reducing cache latency in a coherent cache system.
摘要翻译： 用于形成相干高速缓存系统的一部分的数据处理设备包括用于执行数据处理操作的至少一个主设备和耦合到该至少一个主设备的高速缓存，并且被配置为存储由该至少一个主站访问的数据值 设备执行数据处理操作。 高速缓存一致性电路响应来自相干高速缓存系统的另一部分的一致性请求，以引起关于存储在高速缓存中的至少一个数据值的一致性动作。 响应于一致性动作导致高速缓存中至少一个数据值无效的指示，使用重新读取控制电路来发起将该至少一个数据值重新读取到高速缓存中。 这种机制导致数据重新取入缓存以由响应于来自相干高速缓存系统的另一部分的一致性请求而执行的一致性动作来触发，而不是依赖于由至少一个主设备采取的任何动作，从而 提供了一种非常灵活和有效的机制来减少一致的缓存系统中的缓存延迟。
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公开(公告)号：US08132254B2
公开(公告)日：2012-03-06
申请号：US11889644
申请日：2007-08-15
IPC分类号： G06F21/00
摘要： A data processing apparatus and method for protecting system control registers is provided. Processing logic is providing for executing software routines and a plurality of system control registers are used to store access control information for a plurality of system resources available to the processing logic when executing at least some of those software routines. Additionally, at least one write control register is provided, with each field of that register being associated with one or more of the system control registers. Disable control logic is used to generate a disable signal, and when that disable signal is clear access control information can be written into the system control registers, and write restriction data can be written into each of the fields of the at least one write control register. Then, when the disable control logic sets the disable signal, the at least one write control register becomes read only, and for each field that has write restriction data therein those associated system control registers indicated by the write restriction data also become read only. This mechanism provides a very flexible approach for programming which system control registers are to be treated as read only registers.
摘要翻译： 提供一种用于保护系统控制寄存器的数据处理装置和方法。 处理逻辑正在提供执行软件程序，并且当执行这些软件程序中的至少一些时，多个系统控制寄存器用于存储可用于处理逻辑的多个系统资源的访问控制信息。 此外，提供至少一个写入控制寄存器，该寄存器的每个字段与一个或多个系统控制寄存器相关联。 禁止控制逻辑用于产生禁用信号，当禁用信号清除时，访问控制信息可以写入系统控制寄存器，写入限制数据可写入至少一个写入控制寄存器的每个字段 。 然后，当禁用控制逻辑设置禁止信号时，至少一个写入控制寄存器变为只读，并且对于其中具有写入限制数据的每个字段，由写入限制数据指示的那些相关联的系统控制寄存器也变为只读。 这种机制提供了非常灵活的编程方式，哪些系统控制寄存器被视为只读寄存器。
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公开(公告)号：US20120042136A1
公开(公告)日：2012-02-16
申请号：US13067805
申请日：2011-06-28
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30134 , G06F9/3824
摘要： A data processing system 2 includes a stack pointer register 26, 28, 30, 32 storing a stack pointer value for use in stack access operations to a stack data store 44, 46, 48, 50. Stack alignment checking circuitry 36 which is selectively disabled may be provided to check memory address alignment of the stack pointer value associated with a stack memory access. The action of the stack alignment checking circuitry 36 is independent of any further other alignment checking performed in respect of all memory accesses. Thus, general alignment checking circuitry 38 may be provided and independently selectively disabled in respect of any memory access.
摘要翻译： 数据处理系统2包括堆栈指针寄存器26,28,30,32，其存储用于堆栈访问操作到堆栈数据存储器44,46,48,50的堆栈指针值。堆栈对齐检查电路36被选择性地禁用 可以提供以检查与堆栈存储器访问相关联的堆栈指针值的存储器地址对齐。 堆栈对齐检查电路36的动作独立于关于所有存储器访问执行的任何另外的其它对准检查。 因此，可以提供一般对准检查电路38并且关于任何存储器访问独立地选择性地禁用。
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89.发明申请Data processing apparatus and method for switching a workload between first and second processing circuitry 有权用于在第一和第二处理电路之间切换工作负载的数据处理装置和方法公开(公告)号：US20110213934A1
公开(公告)日：2011-09-01
申请号：US12659234
申请日：2010-03-01
CPC分类号： G06F9/5088 , G06F1/3293 , G06F9/5094 , Y02D10/122 , Y02D10/22 , Y02D10/32 , Y02D50/20
摘要： A data processing apparatus and method are provided for switching performance of a workload between two processing circuits. The data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the first processing circuitry being micro-architecturally different from the second processing circuitry. At any point in time, a workload consisting of at least one application and at least one operating system for running that application is performed by one of the first processing circuitry and the second processing circuitry. A switch controller is responsive to a transfer stimulus to perform a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry. During the handover operation, the switch controller causes the source processing circuitry to makes it current architectural state available to the destination processing circuitry, the current architectural state being that state not available from shared memory at a time the handover operation is initiated, and that is necessary for the destination processing circuitry to successfully take over performance of the workload from the source processing circuitry. In addition, the switch controller masks predetermined processor specific configuration information from the at least one operating system such that the transfer of the workload is transparent to that operating system. Such an approach has been found to yield significant energy consumption benefits whilst avoiding complexities associated with providing operating systems with the capability for switching applications between processing circuits.
摘要翻译： 提供一种用于在两个处理电路之间切换工作负载的性能的数据处理装置和方法。 该数据处理装置具有与第二处理电路架构上兼容的第一处理电路，但第一处理电路在微架构上不同于第二处理电路。 在任何时间点，由至少一个应用程序和用于运行该应用程序的至少一个操作系统组成的工作负载由第一处理电路和第二处理电路之一执行。 开关控制器响应于传送刺激来执行切换操作以将工作负载的性能从源处理电路传送到目的地处理电路，源处理电路是第一和第二处理电路之一，目的地处理电路是 第一和第二处理电路中的另一个。 在切换操作期间，交换机控制器使得源处理电路使其当前架构状态可用于目的地处理电路，当前架构状态是在切换操作开始时该共享存储器不可用的状态，即 目的地处理电路必须成功地从源处理电路接管工作负载的性能。 另外，交换机控制器从至少一个操作系统屏蔽预定的处理器特定配置信息，使得工作负载的传输对该操作系统是透明的。 已经发现这种方法产生显着的能量消耗益处，同时避免了与提供操作系统相关联的复杂性，其具有在处理电路之间切换应用的能力。
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公开(公告)号：US20110202726A1
公开(公告)日：2011-08-18
申请号：US12656709
申请日：2010-02-12
申请人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Andrew Christopher Rose , Richard Roy Grisenthwaite
发明人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Andrew Christopher Rose , Richard Roy Grisenthwaite
CPC分类号： G06F12/0815 , G06F2212/507 , Y02D10/13
摘要： A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache. Such a mechanism causes the refetch of data into the cache to be triggered by the coherency action performed in response to a coherency request from another portion of the coherent cache system, rather than relying on any actions taken by the at least one master device, thereby providing a very flexible and efficient mechanism for reducing cache latency in a coherent cache system.
摘要翻译： 用于形成相干高速缓存系统的一部分的数据处理设备包括用于执行数据处理操作的至少一个主设备和耦合到该至少一个主设备的高速缓存，并且被配置为存储由该至少一个主站访问的数据值 设备执行数据处理操作。 高速缓存一致性电路响应来自相干高速缓存系统的另一部分的一致性请求，以引起关于存储在高速缓存中的至少一个数据值的一致性动作。 响应于一致性动作导致高速缓存中至少一个数据值无效的指示，使用重新读取控制电路来发起将该至少一个数据值重新读取到高速缓存中。 这种机制导致数据重新取入缓存以由响应于来自相干高速缓存系统的另一部分的一致性请求执行的一致性动作来触发，而不是依赖于由至少一个主设备采取的任何动作，从而 提供了一种非常灵活和有效的机制来减少一致的缓存系统中的缓存延迟。
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