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81.发明授权FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections 有权FPGA集成电路具有嵌入式SRAM存储器块，具有注册的地址和数据输入部分公开(公告)号：US06211695B1
公开(公告)日：2001-04-03
申请号：US09235615
申请日：1999-01-21
IPC分类号： G06F738
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has a registered address port for capturing received address signals in response to further-received, address-validating clock signals. Interconnect resources are provided for conveying the address-validating clock signals to address-changing circuitry so that a next address can be generated safely in conjunction with the capturing by the registered address port of a previous address signal.
摘要翻译： 具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。 每个嵌入式存储块具有用于响应于进一步接收的地址确认时钟信号来捕获接收到的地址信号的注册地址端口。 提供互连资源用于将地址确认的时钟信号传送到地址改变电路，使得可以结合由先前地址信号的注册地址端口的捕获而安全地生成下一个地址。
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公开(公告)号：US06191612B1
公开(公告)日：2001-02-20
申请号：US09196449
申请日：1998-11-19
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17744
摘要： A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs). An inter-connect network provides efficient and flexible routing of control signals from VGBs to IOBs. Control signals may include individual control signals to a predetermined IOB or common control signals to a plurality of IOBs. The inter-connect network includes vertical and horizontal inter-connect channels. The inter-connect channels are coupled to switch boxes having line segments or stubs. The line segments are coupled to an IOB control multiplexer which output control signals to IOBs. The use of stubs allows for efficient and flexible use of interconnect resources.
摘要翻译： 现场可编程门阵列（FPGA）装置包括多个输入/输出块（IOB）和可变粒子块（VGB）。 互连网络提供从VGB到IOB的控制信号的有效且灵活的路由选择。 控制信号可以包括到预定IOB的单独控制信号或者与多个IOB的公共控制信号。 互连网络包括垂直和水平互连通道。 互连通道耦合到具有线段或短截线的开关盒。 线段耦合到IOB控制多路复用器，其将控制信号输出到IOB。 使用存根可以有效和灵活地使用互连资源。
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83.发明授权
公开(公告)号：US6127843A
公开(公告)日：2000-10-03
申请号：US996049
申请日：1997-12-22
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes plural columns of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each logic function unit (VGB) is organized to process a nibble of data. Each embedded memory block is multi-ported and organized to store addressable nibbles of data. Interconnect resources are provided for efficiently transferring nibbles of data between the logic function units (VGB's) and corresponding memory blocks. Further interconnect resources (SVIC's) are provided for supplying address and control signals to each memory block. In one embodiment each memory block has at least one read-only port and at least one read/write port that are individually addressable and individually switchable into high output impedance tri-state modes.
摘要翻译： 具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多列嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。 每个逻辑功能单元（VGB）被组织以处理数据的半字节。 每个嵌入式存储器块都是多端口的并被组织以存储可寻址的数据的半字节。 提供互连资源，用于在逻辑功能单元（VGB）和相应的存储块之间有效传输数据的半字节。 提供了进一步的互连资源（SVIC），用于向每个存储块提供地址和控制信号。 在一个实施例中，每个存储器块具有至少一个只读端口和至少一个读/写端口，其可单独寻址并且可单独切换到高输出阻抗三态模式。
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84.发明授权FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode 有权具有嵌入式sram存储器块的FPGA集成电路，每个具有静态和动态可控的读取模式
公开(公告)号：US06081473A
公开(公告)日：2000-06-27
申请号：US212331
申请日：1998-12-15
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals, including a read-mode (RMODE) control signal that switches the memory block between synchronous and asynchronous data transfer modes. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.
摘要翻译： 具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。 每个嵌入式存储块具有用于捕获接收到的地址信号的地址端口和用于捕获所提供的控制信号的控制端口，包括在同步和异步数据传输模式之间切换存储块的读模式（RMODE）控制信号。 提供互连资源，包括用于以广播或窄播为基础将共享地址和控制信号传送到多个存储器块的存储器控制传送互连信道（MCIC）。
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85.发明授权Flexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circuits 失效FPGA集成电路中的输入/输出块（IOB）和可变晶粒块（VGB）之间的灵活的直接连接
公开(公告)号：US5990702A
公开(公告)日：1999-11-23
申请号：US995612
申请日：1997-12-22
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs). An inter-connect network provides routing of signals between the IOBs and VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. The IOBs are arranged along a top, left, bottom and right side of the plurality of VGBs. An IOB includes a 1) delay for timing input signals, 2) a configurable output latch which may be set or reset responsive to control signals, and 3) transistor for controlling a NOR line. The IOB is programmably configured to the inter-connect network which includes vertical and horizontal inter-connect channels comprising adjacent inter-connect lines. The IOB inputs are connected to adjacent inter-connect lines including 1) direct connect input lines from adjacent super-VGBs, 2) MaxL lines, and 3) dendrite lines from adjacent dendrites. The IOB outputs are connected to 1) MaxL lines, 2) dendrite lines in adjacent dendrites, 3) NOR lines, and 4) direct connect output lines to adjacent super-VGBs. Dendrites for routing signals along the periphery of the plurality of VGBs are positioned between the IOBs and super-VGBs. Dendrites include a plurality of I/O switchboxes and dendrite lines. The I/O switchboxes are coupled to vertical and horizontal inter-connect channels. The inter-connect network includes a direct connect architecture between IOBs and adjacent super-VGBs. Dedicated connections between corner and non-corner IOBs provide direct connect inputs and outputs to and from CBBs in a super-VGB.
摘要翻译： 现场可编程门阵列（FPGA）装置包括多个输入/输出块（IOB）和可变粒子块（VGB）。 互连网络提供IOB和VGB之间的信号路由。 VGB包括具有功能生成资源的多个L组织CBB（可配置逻辑块）。 IOB沿着多个VGB的顶部，左侧，底部和右侧布置。 IOB包括1）用于定时输入信号的延迟，2）响应于控制信号可以被设置或复位的可配置输出锁存器，以及3）用于控制NOR线路的晶体管。 IOB可编程地配置到包括相邻连接线之间的垂直和水平互连通道的互连网络。 IOB输入连接到相邻的互连线，包括1）直接连接相邻超VGB的输入线，2）MaxL线，以及3）相邻枝晶的枝晶线。 IOB输出连接到1）MaxL线，2）相邻枝晶中的枝晶线，3）NOR线，以及4）将输出线直接连接到相邻的超VGB。 沿着多个VGB的周边路由信号的树枝状晶体位于IOB和超级VGB之间。 树枝包括多个I / O开关盒和枝晶线。 I / O开关盒耦合到垂直和水平互连通道。 互连网络包括IOB和相邻超级VGB之间的直接连接体系结构。 转角和非拐角IOB之间的专用连接可在超级VGB中向CBB提供直接连接输入和输出。
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86.发明授权
公开(公告)号：US5811987A
公开(公告)日：1998-09-22
申请号：US740948
申请日：1996-11-05
申请人： Benjamin Howard Ashmore, Jr. , Jeffery Mark Marshall , Bryon Irwin Moyer , John David Porter , Nicholas A. Schmitz , Bradley A. Sharpe-Geisler
发明人： Benjamin Howard Ashmore, Jr. , Jeffery Mark Marshall , Bryon Irwin Moyer , John David Porter , Nicholas A. Schmitz , Bradley A. Sharpe-Geisler
IPC分类号： H03K3/037 , H03K3/356 , H03K19/173 , H03K19/177 , H03K19/21 , H03K7/38
CPC分类号： H03K3/037 , H03K19/1736 , H03K19/17704 , H03K19/17728 , H03K19/1774 , H03K19/17772 , H03K19/215 , H03K3/0375 , H03K3/356156
摘要： A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.
摘要翻译： 复合非常高密度可编程逻辑器件中的可编程逻辑块的块时钟和初始化电路为可编程逻辑块中的元件生成多个块时钟信号和块初始化信号。 块时钟和初始化电路包括块时钟发生器电路和块初始化电路。 块时钟发生器电路以多个乘积项和多个时钟信号作为输入信号接收第一组乘积项。 响应于输入信号，块时钟发生器电路在多个块时钟线上产生输出信号。 块初始化电路接收多个乘积项中的第二组乘积项作为输入信号。 响应于输入信号，块初始化电路在块初始化线上产生多个输出信号。
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87.发明授权Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device 失效用于在非常高密度可编程逻辑器件中提供多个分层信号路径的方法
公开(公告)号：US5789939A
公开(公告)日：1998-08-04
申请号：US653186
申请日：1996-05-24
IPC分类号： H03K19/177 , H03K19/082 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/17704
摘要： A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix. The CPLD in addition includes a third hierarchical level circuit having third hierarchial level resources connected to the second hierarchical level resources where a third hierarchical level signal path utilizes the third, second, and first hierarchical level resources. The third hierarchical level resources include a programmable global switch matrix having global switch matrix lines programmably connected to and disconnected from lines of the programmable segment switch matrix.
摘要翻译： 一种非常高密度的复杂可编程逻辑器件（CPLD）具有多个层级信号路径。 层次结构的最低层次与所有更高层次是独立的。 类似地，中间级别与所有较高级别无关，并且仅利用与最低和中级层级相关联的CPLD的资源。 第一层级资源包括具有多个输入线和多条输出线的可编程逻辑块以及连接到可编程逻辑块的多条输入线的可编程块开关矩阵。 第二层级资源包括连接到可编程块开关矩阵的多个输入线的可编程段开关矩阵。 CPLD另外包括具有连接到第二层级资源的第三层级资源的第三层级电路，其中第三层级信号路径利用第三，第二和第一层级资源。 第三层级资源包括可编程全局开关矩阵，其具有可编程地连接到可编程段开关矩阵的线路并与其断开的全局开关矩阵线。
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公开(公告)号：US5570046A
公开(公告)日：1996-10-29
申请号：US453184
申请日：1995-05-30
IPC分类号： H01L23/50 , H01L21/822 , H01L23/495 , H01L27/04 , H03K17/693 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/177 , H03K3/26
CPC分类号： H01L23/49541 , H01L23/495 , H03K19/00361 , H03K19/018507 , H01L2924/0002
摘要： A lead frame with separate noisy and quiet V.sub.SS leads terminating in a single pin and separate noisy and quiet V.sub.DD leads terminating in a single pin. Each noisy lead portion has a line width greater than its corresponding quiet lead portion to reduce noise in the quiet lead portion. Further, line lengths of the noisy and quiet lead portions for the V.sub.SS leads are made longer than the noisy and quiet lead portions for the V.sub.DD leads, or in other words the paddle is moved toward the V.sub.SS leads to reduce ground bounce. Additionally, the noisy and quiet leads overlie a floating conductive plane to further reduce inductance.
摘要翻译： 具有单独噪声和静音VSS引线的引线框架终端于单个引脚，并且单独的噪声和静音VDD引脚终止于单个引脚。 每个有噪声的引线部分具有大于其对应的安静引线部分的线宽，以减小安静引线部分中的噪声。 此外，VSS引线的噪声和安静引线部分的线路长度比VDD引线的噪声和静音引线部分长，或换句话说，桨片朝向VSS引线移动以减少接地反弹。 此外，噪声和静音导线覆盖浮动导电平面以进一步降低电感。
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公开(公告)号：US5495195A
公开(公告)日：1996-02-27
申请号：US341499
申请日：1994-11-17
IPC分类号： H03K19/00 , H03K19/017 , H03K19/0185 , H03K17/16 , H03K17/62
CPC分类号： H03K19/0016 , H03K19/01721 , H03K19/018507
摘要： An output buffer circuit for a high density programmable logic device. The output buffer includes inverters having n-channel pull up and pull down transistors for driving pull up and pull down transistors providing the buffer output. By utilizing inverters with n-channel replacing p-channel transistors, crowbar resulting from a different number of inverters required to drive the pull up and pull down transistors which provide the buffer output is prevented. By utilizing n-channel rather than p-channel transistors, mobility is increased and Miller capacitance is reduced, reducing loading of the buffer input. To provide the rail-to-rail voltage of p-channel transistors which can further increase switching speed, p-channel pull up transistors are provided with circuitry to turn the p-channel transistors on after the n-channel transistors have turned on and turn the p-channel transistors off after the buffer output switches. To further increase switching speed, the buffer includes circuitry to reduce voltage on the gates of the pull up or pull down transistors providing the buffer output after the p-channel transistor driving its gate turns off. To enable control of additional power consumption occurring with increased buffer operation speed, the buffer provides a selectable fast/slow mode wherein features of the buffer which increase operation speed may be selectively enabled or disabled.
摘要翻译： 一种用于高密度可编程逻辑器件的输出缓冲电路。 输出缓冲器包括具有n沟道上拉和下拉晶体管的反相器，用于驱动上拉和提供缓冲器输出的下拉晶体管。 通过利用具有n沟道取代p沟道晶体管的反相器，可以防止由驱动上拉所需的不同数量的反相器产生的撬棒和下拉提供缓冲器输出的晶体管。 通过利用n沟道而不是p沟道晶体管，迁移率增加，并且米勒电容减小，减少了缓冲器输入的负载。 为了提供可以进一步提高开关速度的p沟道晶体管的轨到轨电压，p沟道上拉晶体管设置有电路，以在n沟道晶体管导通和转换之后导通p沟道晶体管 缓冲器输出开关后的p沟道晶体管关闭。 为了进一步提高开关速度，缓冲器包括用于在p沟道晶体管驱动其栅极截止之后降低上拉或下拉晶体管的栅极上提供缓冲器输出的电压的电路。 为了能够以增加的缓冲器操作速度来控制额外的功率消耗，缓冲器提供可选择的快/慢模式，其中可以选择性地启用或禁用增加操作速度的缓冲器的特征。
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公开(公告)号：US4855711A
公开(公告)日：1989-08-08
申请号：US068192
申请日：1987-06-29
CPC分类号： G08B13/1663 , A63B71/0605 , A63B2071/0611
摘要： An impact detection apparatus (10) includes a device that utilizes multiple sensor elements (11) to determine whether or not a ball lands in or out on a tennis court (12). The sensor positions (13-134) are adjacent to the various boundary lines of the tennis court (12). The sensor elements (11) are layered devices which, when compressed, generate an electrical impulse. The impulse is then analyzed through various signal processing means so that an impact caused a sensor (11) to be compressed may be characterized as being a ball, a footstep, or some other object. In this way, near-simultaneous impacts of a ball and a footstep can be distinguished. If the impact is characterized as a ball that has landed out, a control console (206) will give a visual and/or audible signal so that players, and officials if present, are informed that the ball was out.
摘要翻译： 冲击检测装置（10）包括利用多个传感器元件（11）来确定球是否在网球场（12）上进出的设备。 传感器位置（13-134）与网球场（12）的各种边界线相邻。 传感器元件（11）是被压缩时产生电脉冲的分层器件。 然后通过各种信号处理装置分析脉冲，使得传感器（11）被压缩的冲击可被表征为球，脚步或其它物体。 以这种方式，可以区分近乎同时的球和脚步的影响。 如果影响被描述为已经降落的球，则控制台（206）将给出视觉和/或听觉信号，使得球员和官员（如果存在）被通知球已经出来。
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