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    SEMICONDUCTOR MEMORY DEVICE CAPABLE OF LOWERING A WRITE VOLTAGE
    81.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE CAPABLE OF LOWERING A WRITE VOLTAGE 有权
    可降低写电压的半导体存储器件

    公开(公告)号：US20090316479A1

    公开(公告)日：2009-12-24

    申请号：US12407295

    申请日：2009-03-19

    申请人： Noboru Shibata

    发明人： Noboru Shibata

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10

    摘要： A memory cell array is configured so that a plurality of memory cells storing one value of an n value (n is a natural number more than 2) are arranged in a matrix. A control circuit controls the voltage of a word line and a bit line in accordance with input data. The control circuit supplies a first voltage to a word line of a selected cell in a write operation, and supplies a second voltage to at least one word line adjacent to the selected cell. Thereafter, the control circuit changes a voltage of the at least one word line adjacent to the selected cell from the second voltage to a third voltage (second voltage

    摘要翻译： 存储单元阵列被配置为使得存储n值（n是大于2的自然数）的一个值的多个存储单元被布置成矩阵。 控制电路根据输入数据控制字线和位线的电压。 控制电路在写操作中将第一电压提供给所选单元的字线，并将第二电压提供给与所选单元相邻的至少一个字线。 此后，控制电路将与所选择的单元相邻的至少一个字线的电压从第二电压改变为第三电压（第二电压<第三电压），并且还改变所选单元的字线的电压 从第一电压到第四电压（第一电压<第四电压）。

    High-speed verifiable semiconductor memory device
    82.
    发明授权
    High-speed verifiable semiconductor memory device 有权
    高速可验证半导体存储器件

    公开(公告)号：US07573750B2

    公开(公告)日：2009-08-11

    申请号：US12210585

    申请日：2008-09-15

    申请人： Noboru Shibata

    发明人： Noboru Shibata

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3436 ,  G11C16/3404

    摘要： A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing.

    摘要翻译： 存储单元使用n（n：自然数大于1）阈值电压存储多个数据。 在验证存储器单元是否达到预定阈值电压的验证操作中，电压供应电路向存储器单元的栅极提供预定电压。 连接到存储器单元的一个端子的检测电路将存储器单元的一个端子充电到预定电位。 检测电路基于第一检测定时检测存储单元的一个端子的电压，并且还基于第二检测定时检测存储单元的一个端子的电压。

    SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CORRECTING A READ LEVEL PROPERLY
    83.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CORRECTING A READ LEVEL PROPERLY 有权
    可修正读取电平的半导体存储器件

    公开(公告)号：US20090190399A1

    公开(公告)日：2009-07-30

    申请号：US12416750

    申请日：2009-04-01

    申请人： Noboru Shibata ,  Hiroshi Sukegawa

    发明人： Noboru Shibata ,  Hiroshi Sukegawa

    IPC分类号： G11C16/02 ,  G11C16/06

    CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/5646 ,  G11C2211/565

    摘要： In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.

    摘要翻译： 在存储单元阵列中，存储多个位的多个存储单元被连接到多个字线和多个位线并且以矩阵形式排列。 控制部分读取与存储单元阵列中的第一存储器单元相邻的第二存储单元的阈值电平，根据从第二存储器单元读取的阈值电平确定校正电平，将所确定的校正电平加到读出电平 第一存储器单元，然后读取第一存储器单元的阈值电平。 存储部存储校正等级。

    Semiconductor memory device capable of correcting a read level properly
    84.
    发明授权
    Semiconductor memory device capable of correcting a read level properly 有权
    能够正确地校正读取电平的半导体存储器件

    公开(公告)号：US07525839B2

    公开(公告)日：2009-04-28

    申请号：US11753143

    申请日：2007-05-24

    申请人： Noboru Shibata ,  Hiroshi Sukegawa

    发明人： Noboru Shibata ,  Hiroshi Sukegawa

    IPC分类号： G11C7/10

    CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/5646 ,  G11C2211/565

    摘要： In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.

    摘要翻译： 在存储单元阵列中，存储多个位的多个存储单元被连接到多个字线和多个位线并且以矩阵形式排列。 控制部分读取与存储单元阵列中的第一存储器单元相邻的第二存储单元的阈值电平，根据从第二存储器单元读取的阈值电平确定校正电平，将所确定的校正电平加到读出电平 第一存储器单元，然后读取第一存储器单元的阈值电平。 存储部存储校正等级。

    Semiconductor memory device capable of setting a negative threshold voltage
    85.
    发明授权
    Semiconductor memory device capable of setting a negative threshold voltage 有权
    能够设定负阈值电压的半导体存储器件

    公开(公告)号：US07483304B2

    公开(公告)日：2009-01-27

    申请号：US12055074

    申请日：2008-03-25

    申请人： Noboru Shibata

    发明人： Noboru Shibata

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/3454

    摘要： In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potentials of the word lines and bit lines. The control circuit, when reading data from the memory cell connected to a first one of the bit lines, supplies a first voltage to a second bit line provided next to the first bit line and to a source line of the memory cell array.

    摘要翻译： 在存储单元阵列中，连接到字线和位线的多个存储单元被布置成矩阵。 控制电路控制字线和位线的电位。 控制电路当从连接到第一位线的存储单元读取数据时，将第一电压提供给位于第一位线旁边的第二位线和存储单元阵列的源极线。

    Semiconductor memory device with a voltage generating circuit which generates a plurality of voltages using a small number of items of data
    86.
    发明授权
    Semiconductor memory device with a voltage generating circuit which generates a plurality of voltages using a small number of items of data 有权
    具有电压产生电路的半导体存储器件，其使用少量数据产生多个电压

    公开(公告)号：US07443734B2

    公开(公告)日：2008-10-28

    申请号：US11531920

    申请日：2006-09-14

    申请人： Noboru Shibata

    发明人： Noboru Shibata

    IPC分类号： G11C11/34

    CPC分类号： G11C16/12 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3459

    摘要： In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A storage section stores an initial value of a write voltage corresponding to a first write operation and a correction value for correcting the write voltage. A voltage generating circuit generates a word line write voltage in a first write operation or a second write operation on the basis of the initial value and correction value of the write voltage stored in the storage section.

    摘要翻译： 在存储单元阵列中，连接到字线和位线的多个存储单元被布置成矩阵。 存储部存储对应于第一写入操作的写入电压的初始值和用于校正写入电压的校正值。 电压产生电路基于存储在存储部中的写入电压的初始值和校正值，在第一写入操作或第二写入操作中产生字线写入电压。

    Semiconductor memory device which prevents destruction of data
    88.
    发明授权
    Semiconductor memory device which prevents destruction of data 有权
    防止数据破坏的半导体存储器件

    公开(公告)号：US07394691B2

    公开(公告)日：2008-07-01

    申请号：US11498142

    申请日：2006-08-03

    申请人： Noboru Shibata ,  Hiroshi Sukegawa

    发明人： Noboru Shibata ,  Hiroshi Sukegawa

    IPC分类号： G11C11/34 ,  G11C7/00 ,  G11C29/00

    CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/0483

    摘要： A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data by a first write operation and a second write operation. A read section sets a potential of a word line, and reads data from a memory cell in the memory cell array. If data read by the read section and written in the second write operation includes an uncorrectable error, a control section changes a potential of a word line supplied to the read section when reading data written in the first write operation.

    摘要翻译： 每个存储n个值的多个存储单元（n是不小于3的自然数）以矩阵形式布置在存储单元阵列中，并且每个存储单元与字线和位线连接。 每个存储单元通过第一写操作和第二写操作来存储n值数据。 读取部分设置字线的电位，并从存储器单元阵列中的存储单元读取数据。 如果由读取部分读取并写入第二写入操作的数据包括不可校正的错误，则当读取在第一写入操作中写入的数据时，控制部分改变提供给读取部分的字线的电位。

    Nonvolatile semiconductor memory device
    89.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07295468B2

    公开(公告)日：2007-11-13

    申请号：US11401016

    申请日：2006-04-05

    申请人： Noboru Shibata

    发明人： Noboru Shibata

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

    摘要： A page mode multi-level NAND-type memory employs two different verify levels per data state and comprises a first data storage circuit which is connected to a memory cell and which stores externally inputted data of a first logic level or a second logic level, a second data storage circuit which is connected to the memory cell and which stores the data of the first logic level or second logic level read from the memory cell, and a control circuit which controls the memory cell and the first and second data storage circuits and which reproduces the externally inputted data and writing the data into the memory cell.

    摘要翻译： 页面模式多级NAND型存储器对每个数据状态采用两个不同的验证电平，并且包括连接到存储器单元并且存储外部输入的第一逻辑电平或第二逻辑电平的数据的第一数据存储电路， 第二数据存储电路，连接到存储单元，并存储从存储单元读取的第一逻辑电平或第二逻辑电平的数据;以及控制电路，其控制存储单元以及第一和第二数据存储电路， 再现外部输入的数据并将数据写入存储单元。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    90.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20070133291A1

    公开(公告)日：2007-06-14

    申请号：US11610193

    申请日：2006-12-13

    申请人： Yasuyuki FUKUDA ,  Noboru Shibata

    发明人： Yasuyuki FUKUDA ,  Noboru Shibata

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/04 ,  G11C29/82

    摘要： A nonvolatile semiconductor memory device of the present invention is characterized in that, when data is written to a flag cell area, every other flag cell in the direction of one bit line BL among a plurality of flag cells 15 connected to the bit line BL is written with data and every other flag cell in the direction of one word line WL among a plurality of flag cells 15 connected to the word line WL is written with data. The arrangement as described above prevents a flag cell 15 from being influenced by the capacitive coupling of a neighboring flag cell 15 adjacent to the flag cell 15 in the direction of the word line WL. Thus, data (flag data) memorized by the flag cell 15 can have improved reliability.

    摘要翻译： 本发明的非易失性半导体存储器件的特征在于，当数据被写入标志单元区域时，连接到位线BL的多个标志单元15中的一个位线BL的方向上的每隔一个标志单元是 在与字线WL连接的多个标志单元15中的一个字线WL的方向上用数据和每隔一个的标志单元写入数据。 如上所述的布置防止了标志单元15受到在字线WL的方向上与标志单元15相邻的相邻标记单元15的电容耦合的影响。 因此，由标志单元15存储的数据（标志数据）可以提高可靠性。