公开(公告)号：US20110262681A1

公开(公告)日：2011-10-27

申请号：US13093137

申请日：2011-04-25

申请人： Taro Nishiguchi ,  Shin Harada ,  Hiroki Inoue ,  Makoto Sasaki

发明人： Taro Nishiguchi ,  Shin Harada ,  Hiroki Inoue ,  Makoto Sasaki

IPC分类号： C30B23/00 ,  B32B3/14

CPC分类号： H01L29/7802 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02002 ,  H01L29/1608 ,  H01L29/66068

摘要： A carbon layer is formed on a first region of a main surface of a material substrate. On the material substrate, first and second single-crystal layers are arranged such that each of a first backside surface of the first single-crystal layer and a second backside surface of the second single-crystal layer has a portion facing a second region of the main surface of the material substrate and such that a gap between a first side surface of the first single-crystal layer and a second side surface of the second single-crystal layer is located over the carbon layer. By heating the material substrate and the first and second single-crystal layers, a base substrate connected to each of the first and second backside surfaces is formed. In this way, voids can be prevented from being formed in the silicon carbide substrate having such a plurality of single-crystal layers.

摘要翻译： 在材料基板的主表面的第一区域上形成碳层。 在材料基板上，第一和第二单晶层被布置成使得第一单晶层的第一背面和第二单晶层的第二背面中的每一个具有面向第一单晶层的第二区域的部分 使得第一单晶层的第一侧表面和第二单晶层的第二侧表面之间的间隙位于碳层的上方。 通过加热材料基板和第一和第二单晶层，形成连接到第一和第二背面中的每一个的基底基板。 以这种方式，可以防止在具有多个单晶层的碳化硅衬底中形成空隙。

公开(公告)号：US20110175108A1

公开(公告)日：2011-07-21

申请号：US13005719

申请日：2011-01-13

申请人： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

发明人： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

IPC分类号： H01L33/18

CPC分类号： H01L33/16 ,  H01L33/007 ,  H01L33/32

摘要： A silicon carbide substrate has a first layer facing a semiconductor layer and a second layer stacked on the first layer. Dislocation density of the second layer is higher than dislocation density of the first layer. Thus, quantum efficiency and power efficiency of a light-emitting device can both be high.

摘要翻译： 碳化硅衬底具有面向半导体层的第一层和堆叠在第一层上的第二层。 第二层的位错密度高于第一层的位错密度。 因此，发光装置的量子效率和功率效率都可以高。

公开(公告)号：US20100208630A1

公开(公告)日：2010-08-19

申请号：US12600185

申请日：2008-05-09

申请人： Fumitaka Nakahara ,  Shin Harada ,  Kazuhiro Takahashi

发明人： Fumitaka Nakahara ,  Shin Harada ,  Kazuhiro Takahashi

IPC分类号： H04L5/16 ,  G06F17/30

CPC分类号： H04M3/42221 ,  H04M2207/18 ,  H04W4/10 ,  H04W76/45

摘要： A half-duplex communication system that allows a user terminal to confirm past communication contents even during a series of half-duplex communications is provided. The system includes a communication record database in which all communication contents of half-duplex communications are stored together with identifiers thereof. A half-duplex communication device for controlling half-duplex communications includes a communication record control device which receives a communication content, transmits the communication content together with the identifier thereof to the communication record database so as to store it therein, and reads out the communication record therein. In response to a communication record readout request, the half-duplex communication device reads out a communication record in place of transmitting the communication content to a user terminal.

摘要翻译： 提供了即使在一系列半双工通信期间也允许用户终端确认过去通信内容的半双工通信系统。 该系统包括通信记录数据库，其中半双工通信的所有通信内容与其标识符一起存储。 用于控制半双工通信的半双工通信设备包括：通信记录控制设备，其接收通信内容，将通信内容与其标识符一起发送到通信记录数据库，以便将其存储在其中，并读出通信 在其中记录。 响应于通信记录读出请求，半双工通信设备将用于发送通信内容的通信记录读出到用户终端。

公开(公告)号：US20100035420A1

公开(公告)日：2010-02-11

申请号：US12517735

申请日：2007-11-29

申请人： Hideto Tamaso ,  Kazuhiro Fujikawa ,  Shin Harada

发明人： Hideto Tamaso ,  Kazuhiro Fujikawa ,  Shin Harada

IPC分类号： H01L21/265

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068

摘要： A method of manufacturing a semiconductor device includes a first step of forming an ion implantation mask on a portion of a surface of a semiconductor; a second step of implanting ions of a first dopant into at least a portion of an exposed region of the surface of the semiconductor other than the region where the ion implantation mask is formed, to form a first dopant implantation region; a third step of, after forming the first dopant implantation region, removing a portion of the ion implantation mask to increase the exposed region of the surface of the semiconductor; and a fourth step of implanting ions of a second dopant into at least a portion of the increased exposed region of the surface of the semiconductor to form a second dopant implantation region.

摘要翻译： 一种制造半导体器件的方法包括：在半导体表面的一部分上形成离子注入掩模的第一步骤; 将第一掺杂剂的离子注入除了形成离子注入掩模的区域之外的半导体表面的暴露区域的至少一部分中的第二步骤，以形成第一掺杂剂注入区域; 第三步骤，在形成第一掺杂剂注入区域之后，去除一部分离子注入掩模以增加半导体表面的暴露区域; 以及第四步骤，将第二掺杂剂的离子注入所述半导体表面的增加的暴露区域的至少一部分中，以形成第二掺杂剂注入区域。

公开(公告)号：US20080277696A1

公开(公告)日：2008-11-13

申请号：US12179320

申请日：2008-07-24

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/808

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

公开(公告)号：US20070243893A1

公开(公告)日：2007-10-18

申请号：US11712493

申请日：2007-03-01

申请人： Kazuhiro Takahashi ,  Yoshihiro Ono ,  Shin Harada ,  Takashi Shiraki ,  Takehiko Kashiwagi ,  Junpei Kamimura

发明人： Kazuhiro Takahashi ,  Yoshihiro Ono ,  Shin Harada ,  Takashi Shiraki ,  Takehiko Kashiwagi ,  Junpei Kamimura

IPC分类号： H04B7/00

CPC分类号： H04W4/10 ,  H04W72/005 ,  H04W76/45 ,  H04W88/14 ,  H04W88/18

摘要： The object of the present invention is to realize a method and a server which enable insertion of advertisement even in voice communication including multimedia communication. The server is configured as a server for managing PoC communication among multiple terminals, comprising: a right-to-speak management section for managing the right to speak of the multiple terminals; a data distribution section for transmitting and receiving data to and from the multiple terminals; and an advertisement control section for storing advertisement data and transmitting the stored advertisement data to the multiple terminals via the data distribution section.

摘要翻译： 本发明的目的是实现即使在包括多媒体通信的语音通信中也能插入广告的方法和服务器。 该服务器被配置为用于管理多个终端之间的PoC通信的服务器，包括：用于管理多个终端的发言权的一个发言权管理部分; 数据分配部，用于向多个终端发送数据和从多个终端接收数据; 以及广告控制部分，用于存储广告数据并经由数据分发部分将存储的广告数据发送到多个终端。

公开(公告)号：US06870189B1

公开(公告)日：2005-03-22

申请号：US10168265

申请日：2000-09-11

申请人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L21/337 ,  H01L29/24 ,  H01L29/772 ,  H01L29/808 ,  H01L31/0312 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/0843 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66901 ,  H01L29/66909 ,  H01L29/7722 ,  H01L29/808 ,  H01L29/8083

摘要： A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conductivity type provided on a surface of a semiconductor substrate, a source region (1) of a first conductivity type, a channel region (10) of the first conductivity type that adjoins the source region, a confining region (5) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region (3) of the first conductivity type provided on a reverse face, and a drift region (4) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain. A concentration of an impurity of the first conductivity type in the drift region and the channel region is lower than a concentration of an impurity of the first conductivity type in the source region and the drain region and a concentration of an impurity of the second conductivity type in the confining region.

摘要翻译： 提供了一种结型场效应晶体管（JFET），其具有能够以低损耗工作并且几乎没有变化的高电压电阻，高电流切换操作。 该JFET设置有设置在半导体衬底的表面上的第二导电类型的栅极区域（2），第一导电类型的源极区域（1），第一导电类型的沟道区域（10） 源极区域，邻接栅极区域并限制沟道区域的第二导电类型的约束区域（5），设置在反面上的第一导电类型的漏极区域（3）和漂移区域（4） 的第一导电类型，其连续地位于从通道到漏极的衬底的厚度方向上。 漂移区域和沟道区域中的第一导电类型的杂质的浓度低于源极区域和漏极区域中的第一导电类型的杂质浓度和第二导电类型的杂质浓度 在限制区域。

公开(公告)号：US09255344B2

公开(公告)日：2016-02-09

申请号：US13605265

申请日：2012-09-06

申请人： Shin Harada ,  Shinsuke Fujiwara ,  Taro Nishiguchi

发明人： Shin Harada ,  Shinsuke Fujiwara ,  Taro Nishiguchi

IPC分类号： C30B23/00 ,  C30B29/36 ,  C30B35/00 ,  H01L21/02

CPC分类号： C30B23/025 ,  C30B23/005 ,  C30B29/36 ,  C30B35/007 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02631

摘要： A silicon carbide substrate capable of stably forming a device of excellent performance, and a method of manufacturing the same are provided. A silicon carbide substrate is made of a single crystal of silicon carbide, and has a width of not less than 100 mm, a micropipe density of not more than 7 cm−2, a threading screw dislocation density of not more than 1×104 cm−2, a threading edge dislocation density of not more than 1×104 cm−2, a basal plane dislocation density of not more than 1×104 cm−2, a stacking fault density of not more than 0.1 cm−1, a conductive impurity concentration of not less than 1×1018 cm−3, a residual impurity concentration of not more than 1×1016 cm−3, and a secondary phase inclusion density of not more than 1 cm−3.

摘要翻译： 提供能够稳定地形成优异性能的器件的碳化硅衬底及其制造方法。 碳化硅衬底由碳化硅单晶制成，宽度不小于100mm，微管密度不超过7cm -2，螺纹位错密度不大于1×104cm -2，螺纹刃位错密度不大于1×104cm-2，基面位错密度不大于1×104cm-2，堆垛层错密度不大于0.1cm-1，导电 杂质浓度不小于1×1018 cm -3，残留杂质浓度不大于1×1016 cm-3，次相夹杂密度不大于1 cm -3。

公开(公告)号：US09090992B2

公开(公告)日：2015-07-28

申请号：US13257742

申请日：2010-11-12

申请人： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada

发明人： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada

IPC分类号： C30B29/36 ,  C30B23/02

CPC分类号： C30B29/36 ,  C30B23/025

摘要： A seed crystal having a frontside surface and a backside surface is prepared. Surface roughness of the backside surface of the seed crystal is increased. A coating film including carbon is formed on the backside surface of the seed crystal. The coating film and a pedestal are brought into contact with each other with an adhesive interposed therebetween. The adhesive is cured to fix the seed crystal to the pedestal. A single crystal is grown on the seed crystal. Before the growth is performed, a carbon film is formed by carbonizing the coating film.

摘要翻译： 准备具有前表面和背面的晶种。 晶种背面的表面粗糙度增加。 在籽晶的背面形成有包含碳的涂膜。 涂膜和基座之间插入有粘合剂，彼此接触。 固化粘合剂以将晶种固定到基座。 在晶种上生长单晶。 在生长之前，通过碳化涂膜形成碳膜。

公开(公告)号：US08643065B2

公开(公告)日：2014-02-04

申请号：US12919992

申请日：2009-12-11

申请人： Kazuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

发明人： Kazuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

IPC分类号： H01L29/80

CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/8083

摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。 晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。 第一p型区域包括设置成包括上表面的基极区域和突出区域。 基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。 栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。