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    Semiconductor device and method for manufacturing the same
    1.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08643065B2

    公开(公告)日：2014-02-04

    申请号：US12919992

    申请日：2009-12-11

    申请人： Kazuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

    发明人： Kazuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

    IPC分类号： H01L29/80

    CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/8083

    摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

    摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。 晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。 第一p型区域包括设置成包括上表面的基极区域和突出区域。 基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。 栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20100035420A1

    公开(公告)日：2010-02-11

    申请号：US12517735

    申请日：2007-11-29

    申请人： Hideto Tamaso ,  Kazuhiro Fujikawa ,  Shin Harada

    发明人： Hideto Tamaso ,  Kazuhiro Fujikawa ,  Shin Harada

    IPC分类号： H01L21/265

    CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068

    摘要： A method of manufacturing a semiconductor device includes a first step of forming an ion implantation mask on a portion of a surface of a semiconductor; a second step of implanting ions of a first dopant into at least a portion of an exposed region of the surface of the semiconductor other than the region where the ion implantation mask is formed, to form a first dopant implantation region; a third step of, after forming the first dopant implantation region, removing a portion of the ion implantation mask to increase the exposed region of the surface of the semiconductor; and a fourth step of implanting ions of a second dopant into at least a portion of the increased exposed region of the surface of the semiconductor to form a second dopant implantation region.

    摘要翻译： 一种制造半导体器件的方法包括：在半导体表面的一部分上形成离子注入掩模的第一步骤; 将第一掺杂剂的离子注入除了形成离子注入掩模的区域之外的半导体表面的暴露区域的至少一部分中的第二步骤，以形成第一掺杂剂注入区域; 第三步骤，在形成第一掺杂剂注入区域之后，去除一部分离子注入掩模以增加半导体表面的暴露区域; 以及第四步骤，将第二掺杂剂的离子注入所述半导体表面的增加的暴露区域的至少一部分中，以形成第二掺杂剂注入区域。

    SILICON CARBIDE SEMICONDUCTOR DEVICE
    3.
    发明申请
    SILICON CARBIDE SEMICONDUCTOR DEVICE 审中-公开
    硅碳化硅半导体器件

    公开(公告)号：US20110175111A1

    公开(公告)日：2011-07-21

    申请号：US13121893

    申请日：2009-08-07

    申请人： Shin Harada ,  Hideto Tamaso ,  Tomoaki Hatayama

    发明人： Shin Harada ,  Hideto Tamaso ,  Tomoaki Hatayama

    IPC分类号： H01L29/24

    CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L21/0485 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/66068 ,  H01L29/808 ,  H01L29/8613

    摘要： Provided is a silicon carbide semiconductor device capable of lowering the contact resistance of an ohmic electrode and achieving high reverse breakdown voltage characteristics. A semiconductor device includes a substrate and a p+ region as an impurity layer. The substrate of the first conductive type (n type) is made of silicon carbide and has a dislocation density of 5×103 cm−2 or less. The p+ region is formed on the substrate, in which the concentration of the conductive impurities having the second conductive type different from the first conductive type is 1×1020 cm3 or more and 5×1021 cm3 or less.

    摘要翻译： 提供了能够降低欧姆电极的接触电阻并实现高反向击穿电压特性的碳化硅半导体器件。 半导体器件包括衬底和作为杂质层的p +区域。 第一导电型（n型）的基板由碳化硅构成，位错密度为5×10 3 cm -2以下。 p +区形成在基板上，其中具有不同于第一导电类型的第二导电类型的导电杂质的浓度为1×1020cm 3以上且5×1021cm 3以下。

    METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE
    5.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE 审中-公开
    制造半导体基板的方法

    公开(公告)号：US20120003811A1

    公开(公告)日：2012-01-05

    申请号：US13254947

    申请日：2010-09-28

    申请人： Makoto Sasaki ,  Shin Harada ,  Taro Noshiguchi ,  Kyoto Okita ,  Hideto Tamaso ,  Yasuo Namikawa

    发明人： Makoto Sasaki ,  Shin Harada ,  Taro Noshiguchi ,  Kyoto Okita ,  Hideto Tamaso ,  Yasuo Namikawa

    IPC分类号： H01L21/04

    CPC分类号： H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02612 ,  H01L21/02656 ,  H01L21/02667 ,  H01L21/047 ,  H01L29/66068

    摘要： A first silicon carbide substrate has a first front-side surface and a first side surface. A second silicon carbide substrate has a second front-side surface and a second side surface. The second side surface is disposed such that a gap having an opening between the first and second front-side surfaces of the first and second silicon carbide substrates is disposed between the first side surface and the second side surface. A closing portion is provided to close the gap over the opening. By depositing sublimates from the first and second side surfaces onto the closing portion, a connecting portion is formed to connect the first and second side surfaces to each other so as to close the opening. After the step of forming the connecting portion, the closing portion is removed.

    摘要翻译： 第一碳化硅衬底具有第一前侧表面和第一侧表面。 第二碳化硅衬底具有第二前侧表面和第二侧表面。 第二侧表面设置成使得在第一和第二碳化硅衬底的第一和第二前侧表面之间具有开口的间隙设置在第一侧表面和第二侧表面之间。 提供封闭部分以封闭开口上的间隙。 通过将第一和第二侧表面的升华物沉积到封闭部分上，形成连接部分以将第一和第二侧表面彼此连接以便关闭开口。 在形成连接部分的步骤之后，去除封闭部分。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20110001144A1

    公开(公告)日：2011-01-06

    申请号：US12919992

    申请日：2009-12-11

    申请人： Kuzuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

    发明人： Kuzuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

    IPC分类号： H01L31/0312 ,  H01L21/337

    CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/8083

    摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

    摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。 晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。 第一p型区域包括设置成包括上表面的基极区域和突出区域。 基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。 栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。

    Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors
    9.
    发明授权
    Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors 失效
    垂直结场效应晶体管，以及垂直结型场效应晶体管的制造方法

    公开(公告)号：US07750377B2

    公开(公告)日：2010-07-06

    申请号：US11770414

    申请日：2007-06-28

    申请人： Takashi Hoshino ,  Shin Harada ,  Kazuhiro Fujikawa ,  Satoshi Hatsukawa ,  Kenichi Hirotsu

    发明人： Takashi Hoshino ,  Shin Harada ,  Kazuhiro Fujikawa ,  Satoshi Hatsukawa ,  Kenichi Hirotsu

    IPC分类号： H01L29/80

    CPC分类号： H01L29/66068 ,  H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66909 ,  H01L29/8083

    摘要： A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.

    摘要翻译： 根据本发明的垂直JFET 1a具有n +型漏极半导体部分2，n型漂移半导体部分3，p +型栅极半导体部分4，n型沟道半导体部分5，n +型源半导体部分 7和p +型栅极半导体部分8.n型漂移半导体部分3放置在n +型漏极半导体部分2的主表面上，并且具有在与主体相交的方向上延伸的第一至第四区域3a至3d 表面。 p +型栅极半导体部分4放置在n型漂移半导体部分3的第一至第三区域3a至3c上.n型沟道半导体部分5沿着p +型栅极半导体部分4放置并且电连接 到n型漂移半导体部分3的第四区域3d。