公开(公告)号：US20220091938A1

公开(公告)日：2022-03-24

申请号：US17539714

申请日：2021-12-01

Applicant: Micron Technology, Inc.

Inventor： Todd M. Buerkle ,  Debra M. Bell ,  Joshua E. Alzheimer

IPC: G06F11/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory device. The memory array may correspond to a set of memory addresses, where each memory address of the set corresponds to a first portion of the memory array (e.g., user data plane) and to a second portion of the memory array (e.g., ECC plane). The second portion may be configured to store ECC data or second user data or metadata based on whether the ECC functionality is enabled or disabled. The memory device may determine a command directed to the memory address of the set is configured to access the first portion or the second portion based on a status of a pin associated with the command.

公开(公告)号：US20220055631A1

公开(公告)日：2022-02-24

申请号：US16997688

申请日：2020-08-19

Applicant: Micron Technology, Inc.

Inventor： Srinivasa Anuradha Bulusu ,  Shannon M. Hansen ,  Debra M. Bell ,  Barbara J. Bailey

IPC: B60W40/08 ,  H04W4/48 ,  H04W4/44 ,  B60W60/00

Abstract: Methods, devices, and systems related to sensor monitoring in a vehicle are described. In an example, a method can include receiving a trained artificial intelligence (AI) model at a memory device in a vehicle, transmitting the trained AI model to a processing resource in the vehicle, receiving, at the processing resource, data associated with a person located in the vehicle from a sensor included in a computing device and data associated with the vehicle from a sensor included in the vehicle, inputting the received data into the AI model at the processing resource, and sending a command in response to an output of the AI model.

公开(公告)号：US11200118B2

公开(公告)日：2021-12-14

申请号：US16554931

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Todd M. Buerkle ,  Debra M. Bell ,  Joshua E. Alzheimer

IPC: G01R31/28 ,  G06F11/10 ,  G11C29/38

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory device. The memory array may correspond to a set of memory addresses, where each memory address of the set corresponds to a first portion of the memory array (e.g., user data plane) and to a second portion of the memory array (e.g., ECC plane). The second portion may be configured to store ECC data or second user data or metadata based on whether the ECC functionality is enabled or disabled. The memory device may determine a command directed to the memory address of the set is configured to access the first portion or the second portion based on a status of a pin associated with the command.

公开(公告)号：US11042436B2

公开(公告)日：2021-06-22

申请号：US16554913

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Aaron Jannusch ,  Brett K. Dodds ,  Debra M. Bell ,  Joshua E. Alzheimer ,  Scott E. Smith

IPC: G11C29/00 ,  G06F11/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

公开(公告)号：US20210158863A1

公开(公告)日：2021-05-27

申请号：US16693949

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/409 ,  G11C29/00

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory row and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.

公开(公告)号：US20210064460A1

公开(公告)日：2021-03-04

申请号：US16554913

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Aaron Jannusch ,  Brett K. Dodds ,  Debra M. Bell ,  Joshua M. Alzheimer ,  Scott E. Smith

IPC: G06F11/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

公开(公告)号：US10930335B2

公开(公告)日：2021-02-23

申请号：US16231327

申请日：2018-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

公开(公告)号：US20200343249A1

公开(公告)日：2020-10-29

申请号：US16927717

申请日：2020-07-13

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell

IPC: H01L27/11 ,  G11C11/419 ,  G11C11/412 ,  H01L27/092

Abstract: Some embodiments include an integrated assembly having a first pull-down transistor, a second pull-down transistor, a first pull-up transistor and a second pull-up transistor. The first pull-down transistor has a first conductive-gate-body at a first level, and has an n-channel-device-active-region at a second level vertically offset from the first level. The first pull-up transistor has a second conductive-gate-body at the first level, and has a p-channel-device-active-region at the second level. The second pull-down transistor has a third conductive-gate-body at the second level, and has an n-channel-device-active-region at the first level. The second pull-up transistor has a fourth conductive-gate-body at the second level, and has a p-channel-device-active-region at the first level.

公开(公告)号：US10803926B2

公开(公告)日：2020-10-13

申请号：US16237115

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/406 ,  G11C7/18 ,  H01L25/10 ,  G11C11/4096

Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

公开(公告)号：US10734044B2

公开(公告)日：2020-08-04

申请号：US16103151

申请日：2018-08-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell

IPC: G11C7/22 ,  G11C7/12 ,  G11C11/4076 ,  G11C7/10

Abstract: A write-in date circuit in a semiconductor device may include multiple input buffers, each receiving multiple data bits in a serial data stream. The circuit may include a first circuit coupled to a first and a second input buffers. The first circuit may be further coupled to receive a DQS signal and latch a first data bit selected from the first input buffer or the second input buffer responsive to the DQS signal. The second circuit may be coupled to the first and second input buffers and configured to latch a second data bit selected from the first input buffer or the second input buffer responsive to the DQS signal. The first circuit may latch the first data bit responsive to a rising edge of the DQS signal and the second circuit may latch the second data bit responsive to a falling edge of the DQS signal.