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公开(公告)号:US20220351775A1
公开(公告)日:2022-11-03
申请号:US17867359
申请日:2022-07-18
Applicant: Micron Technology, Inc.
Inventor: Jun Liu
IPC: G11C13/00
Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.
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公开(公告)号:US10790020B2
公开(公告)日:2020-09-29
申请号:US16384557
申请日:2019-04-15
Applicant: Micron Technology, Inc.
Inventor: Jun Liu
Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.
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公开(公告)号:US10777739B2
公开(公告)日:2020-09-15
申请号:US15850632
申请日:2017-12-21
Applicant: Micron Technology, Inc.
Inventor: Jun Liu , Michael P. Violette
IPC: H01L45/00
Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
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公开(公告)号:US20190103556A1
公开(公告)日:2019-04-04
申请号:US16200969
申请日:2018-11-27
Applicant: Micron Technology, Inc.
Inventor: Jun Liu , Kunal R. Parekh
IPC: H01L45/00 , H01L43/12 , H01L43/08 , H01L43/02 , H01L27/24 , H01L21/768 , H01L21/033
CPC classification number: H01L45/16 , H01L21/0337 , H01L21/76807 , H01L21/76816 , H01L27/2472 , H01L43/02 , H01L43/08 , H01L43/12 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/1273 , H01L45/14 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.
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公开(公告)号:US20190051340A1
公开(公告)日:2019-02-14
申请号:US16164606
申请日:2018-10-18
Applicant: Micron Technology, Inc.
Inventor: Jun Liu , Gurtej Sandhu
CPC classification number: G11C11/1675 , G11C11/16 , G11C11/161 , G11C11/1695 , H01L43/02
Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.
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公开(公告)号:US10153431B2
公开(公告)日:2018-12-11
申请号:US15661351
申请日:2017-07-27
Applicant: Micron Technology, Inc.
Inventor: Eugene P. Marsh , Jun Liu
IPC: H01L45/00
Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.
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公开(公告)号:US20180138399A1
公开(公告)日:2018-05-17
申请号:US15850632
申请日:2017-12-21
Applicant: Micron Technology, Inc.
Inventor: Jun Liu , Michael P. Violette
IPC: H01L45/00
Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
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公开(公告)号:US09940989B2
公开(公告)日:2018-04-10
申请号:US15421204
申请日:2017-01-31
Applicant: Micron Technology, Inc.
Inventor: Jun Liu , Gurtej Sandhu
CPC classification number: G11C11/1675 , G11C11/16 , G11C11/161 , G11C11/1659 , H01L29/66007 , H01L43/02 , H01L43/08 , H01L43/12
Abstract: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.
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89.
公开(公告)号:US20180068724A1
公开(公告)日:2018-03-08
申请号:US15798166
申请日:2017-10-30
Applicant: Micron Technology, Inc.
Inventor: Jun Liu
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/003 , G11C13/004 , G11C2013/0073 , G11C2013/009 , G11C2213/72 , G11C2213/74
Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.
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公开(公告)号:US20170324034A1
公开(公告)日:2017-11-09
申请号:US15661351
申请日:2017-07-27
Applicant: Micron Technology, Inc.
Inventor: Eugene P. Marsh , Jun Liu
IPC: H01L45/00
CPC classification number: H01L45/085 , H01L45/08 , H01L45/1233 , H01L45/124 , H01L45/1246 , H01L45/1253 , H01L45/1266 , H01L45/14 , H01L45/143 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1683
Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.
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