公开(公告)号：US08508984B2

公开(公告)日：2013-08-13

申请号：US12040801

申请日：2008-02-29

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: G11C11/00

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  H01L43/08

Abstract: A non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, and a free layer formed on top of the barrier layer, wherein the electrical resistivity of the barrier layer is reduced by placing said barrier layer under compressive stress. Compressive stress is induced by either using a compressive stress inducing layer, or by using inert gases at low pressure during the sputtering process as the barrier layer is deposited, or by introducing compressive stress inducing molecules into the molecular lattice of the barrier layer.

Abstract translation: 非易失性磁存储元件包括固定层，形成在固定层顶部上的阻挡层和形成在阻挡层顶部上的自由层，其中阻挡层的电阻率通过将阻挡层 在压应力下。 或者通过使用压缩应力诱导层或在溅射过程中使用惰性气体在溅射过程中作为阻挡层被沉积或通过将压应力诱导分子引入到阻挡层的分子晶格中而引起压缩应力。

公开(公告)号：US08427863B2

公开(公告)日：2013-04-23

申请号：US12986802

申请日：2011-01-07

Applicant: Rajiv Yadav Ranjan ,  Roger Klaus Malmhall ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Roger Klaus Malmhall ,  Parviz Keshtbod

IPC: G11C11/00

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C19/0808 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.

Abstract translation: 公开了一种包括自由层，两个堆叠和磁性隧道结的多态低电流切换磁存储元件（磁存储元件）。 堆叠和磁性隧道结设置在自由层的表面上，磁性隧道结位于堆叠之间。 堆叠在自由层内引导磁畴，产生自由层畴壁。 从堆栈传递到堆栈的电流推动域壁，重新定位自由层内的域壁。 畴壁相对于磁性隧道结的位置对应于唯一的电阻值，并且将电流从堆叠传递到磁性隧道结读取磁存储元件的电阻。 因此，可以通过移动域壁来实现唯一的记忆状态。

公开(公告)号：US20130052752A1

公开(公告)日：2013-02-28

申请号：US13199490

申请日：2011-08-30

Applicant: Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger K. Malmhall

Inventor： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger K. Malmhall

IPC: H01L21/8246

CPC classification number: H01L43/12 ,  H01L29/00

Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.

Abstract translation: 本发明的各种实施例涉及用于制造MRAM装置中的MTJ电池的蚀刻工艺。 各种实施例可以彼此组合使用。 第一实施例在硬掩模和顶电极之间添加硬掩模缓冲层。 第二实施例使用多层蚀刻硬掩模。 第三实施例使用包括第二层如Ta之下的第一Cu层的多层顶电极结构。 第四实施例是用于底部电极去除再沉积材料同时保持更垂直侧壁蚀刻轮廓的两相蚀刻工艺。 在第一阶段中，使用碳质反应离子蚀刻去除底部电极层直到端点。 在第二阶段中，使用惰性气体和/或氧等离子体去除在先前蚀刻工艺期间沉积的聚合物。

公开(公告)号：US08385108B1

公开(公告)日：2013-02-26

申请号：US13429293

申请日：2012-03-23

Applicant: Ebrahim Abedifard ,  Siamack Nemazie ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Siamack Nemazie ,  Parviz Keshtbod

IPC: G11C11/00

CPC classification number: G11C11/14 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697

Abstract: A method of method of writing to a magnetic memory cell includes selecting a magnetic memory cell of a magnetic memory array to be written to, the magnetic memory cell including a pair of MTJs, and setting a bit line (BL) coupled to the magnetic memory cell to a state that causes current to flow through the pair of MTJs in a manner that causes the direction of current flow through one of the MTJs of the pair of MTJs to be in a direction opposite to that of the other MTJ of the pair of MTJs.

Abstract translation: 写入磁存储单元的方法的方法包括选择要写入的磁存储器阵列的磁存储单元，磁存储单元包括一对MTJ，以及设置耦合到磁存储器的位线（BL） 电池导致电流流过该对MTJ的状态，使得电流流过该对MTJ的MTJ之一的电流的方向处于与该对MTJ的另一个MTJ的方向相反的方向 MTJs。

公开(公告)号：US08363457B2

公开(公告)日：2013-01-29

申请号：US12125866

申请日：2008-05-22

Applicant: Parviz Keshtbod

Inventor： Parviz Keshtbod

IPC: G11C11/00

CPC classification number: G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693

Abstract: A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element.

Abstract translation: 感测电路包括具有第一和第二节点的读出放大器电路，通过该第一和第二节点检测磁存储元件。 第一电流源耦合到第一节点，第二电流源耦合到第二节点。 参考磁存储元件具有与之相关联的电阻并且耦合到第一节点，参考磁存储元件从第一电流源接收电流。 具有与其相关联的电阻的至少一个存储元件耦合到第二节点并从第二电流源接收电流。 来自第一电流源的电流和来自第二电流源的电流基本相同。 通过比较至少一个存储元件的电阻与参考磁存储元件的电阻来感测至少一个存储元件的逻辑状态。

公开(公告)号：US08313960B1

公开(公告)日：2012-11-20

申请号：US13371380

申请日：2012-02-10

Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: H01L21/00

CPC classification number: H01L43/12

Abstract: A method of manufacturing a magnetic memory element includes the steps of forming a permanent magnetic layer on top a bottom electrode, forming a pinning layer on top the permanent magnetic layer, forming a magnetic tunnel junction (MTJ) including a barrier layer on top of the pinning layer, forming a top electrode on top of the MTJ, forming a hard mask on top of the top electrode, and using the hard mask to perform a series of etching processes to reduce the width of the MTJ and the top electrode to substantially a desired width, where one of these etching processes is stopped when a predetermined material in the pinning layer is detected thereby avoiding deposition of metal onto the barrier layer of the etching process thereby preventing shorting.

Abstract translation: 一种制造磁存储元件的方法包括以下步骤：在底部电极的顶部形成永久磁性层，在永久磁性层的顶部形成钉扎层，形成包含阻挡层的磁性隧道结（MTJ） 钉扎层，在MTJ的顶部形成顶部电极，在顶部电极的顶部上形成硬掩模，并且使用硬掩模执行一系列蚀刻工艺以将MTJ和顶部电极的宽度减小到基本上 当检测到钉扎层中的预定材料时，这些蚀刻工艺中的一个停止，从而避免金属沉积到蚀刻工艺的阻挡层上，从而防止短路。

公开(公告)号：US08289757B2

公开(公告)日：2012-10-16

申请号：US12778725

申请日：2010-05-12

Applicant: Parviz Keshtbod ,  Ebrahim Abedifard

Inventor： Parviz Keshtbod ,  Ebrahim Abedifard

IPC: G11C11/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/105 ,  H01L27/228

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract translation: 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属并形成在存取晶体管的顶部。 在位于靠近位线的ILD层中形成的金属的顶部上形成磁隧道结（MTJ）。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。

公开(公告)号：US20120230095A1

公开(公告)日：2012-09-13

申请号：US13476879

申请日：2012-05-21

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: G11C11/16

CPC classification number: B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/228 ,  H01L43/08

Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

Abstract translation: 非易失性磁存储元件包括多个层，其中之一是分级的自由层。 分级自由层可以包括各种元素，其中每个元素具有不同的各向异性，或者其可以包括非磁性化合物和磁性区域，其中非磁性化合物形成梯度含量形成独特的形状，例如锥形，菱形或其它形状，并且其厚度 是基于磁性化合物的反应性。

公开(公告)号：US08183652B2

公开(公告)日：2012-05-22

申请号：US11739648

申请日：2007-04-24

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod

IPC: H01L29/82 ,  G11C11/00

CPC classification number: H01L43/10 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228

Abstract: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer formed on top of the tunnel layer, a granular film layer formed on top of the first free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second free layer, and a top electrode formed on top of the cap layer.

Abstract translation: 非易失性电流切换磁存储元件包括底电极，形成在底电极顶部的钉扎层和形成在钉扎层顶部上的固定层。 存储元件还包括形成在钉扎层顶部的隧道层，形成在隧道层顶部上的第一自由层，形成在第一自由层的顶部上的粒状膜层，形成在第一自由层顶部的第二自由层 颗粒膜层，形成在第二自由层顶部上的盖层，以及形成在盖层顶部上的顶部电极。

公开(公告)号：US20120025338A1

公开(公告)日：2012-02-02

申请号：US13253916

申请日：2011-10-05

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: H01L29/82

CPC classification number: B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/228 ,  H01L43/08

Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

Abstract translation: 非易失性磁存储元件包括多个层，其中之一是分级的自由层。 分级自由层可以包括各种元素，其中每个元素具有不同的各向异性，或者其可以包括非磁性化合物和磁性区域，其中非磁性化合物形成梯度含量形成独特的形状，例如锥形，菱形或其它形状，并且其厚度 是基于磁性化合物的反应性。