公开(公告)号：US4868418A

公开(公告)日：1989-09-19

申请号：US151757

申请日：1988-02-03

申请人： Kenichi Imamura ,  Masao Taguchi

发明人： Kenichi Imamura ,  Masao Taguchi

IPC分类号： H03K5/08 ,  H01L29/68 ,  H03K5/02 ,  H03K5/24

CPC分类号： B82Y10/00 ,  H03K5/2418

摘要： A comparator circuit comprises a differential amplifier supplied with a reference signal and an input signal. A resonant-tunneling transistor has a base supplied with an output signal of the differential amplifier. A collector is connected to a first power supply source via a resistor. An emitter is connected to a second power supply source. Therefore, it is possible to simplify a circuit configuration of the comparator circuit and to improve an operation speed of the comparator circuit by outputting an output signal from a connection portion between the resistor and the collector of the transistor.

公开(公告)号：US4801989A

公开(公告)日：1989-01-31

申请号：US16611

申请日：1987-02-19

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： H01L27/108

CPC分类号： H01L27/10829

摘要： In a dynamic random access memory having a trench capacitor, a first conductive layer is formed on all of the inner surface of the trench except for a region adjacent to the opening portion of the trench, a dielectric layer is formed on the first conductive layer exposed in the trench and the surface of the semiconductor substrate, and a second conductive layer of the other conduction type is filled in the trench through the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer constitute a storage capacitor. In this dynamic random access memory, a metal insulator semiconductor transistor is formed in the semiconductor substrate, a source or drain region of the transistor of the other conduction type is in contact with the second conductive layer through the dielectric layer, and the second conductive layer is connected with the source or drain region of the other conduction type.

摘要翻译： 在具有沟槽电容器的动态随机存取存储器中，除了与沟槽的开口部分相邻的区域之外，在沟槽的所有内表面上形成第一导电层，在第一导电层上暴露出介电层 在沟槽和半导体衬底的表面中，另一导电类型的第二导电层通过电介质层填充在沟槽中。 第一导电层，电介质层和第二导电层构成存储电容器。 在该动态随机存取存储器中，在半导体衬底中形成金属绝缘体半导体晶体管，另一导电型晶体管的源区或漏极区通过电介质层与第二导电层接触，第二导电层 与另一导电类型的源极或漏极区域连接。

公开(公告)号：US4622570A

公开(公告)日：1986-11-11

申请号：US615675

申请日：1984-06-01

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： G11C11/401 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  G11C11/34 ,  H01L27/02 ,  H01L29/04

CPC分类号： H01L29/7838 ,  G11C11/404 ,  H01L27/0883 ,  H01L27/10805

摘要： A semiconductor memory device of a one-transistor type is manufactured by using a so-called double-layer technology. The device comprises a buried-channel type transistor having normally-off characteristics and a capacitor having normally-on characteristics to provide high integrated density. An insulating layer between two conductive layers for forming the transistor and the capacitor is relatively thick to provide increased breakdown voltage and reduced parasitic capacitance.

摘要翻译： 通过使用所谓的双层技术制造单晶体管型半导体存储器件。 该器件包括具有常关特性的掩埋沟道型晶体管和具有常开特性以提供高集成度密度的电容器。 用于形成晶体管和电容器的两个导电层之间的绝缘层相对较厚，以提供增加的击穿电压和降低的寄生电容。

公开(公告)号：US08363466B2

公开(公告)日：2013-01-29

申请号：US12976355

申请日：2010-12-22

申请人： Naoharu Shinozaki ,  Masao Taguchi ,  Satoru Sugimoto

发明人： Naoharu Shinozaki ,  Masao Taguchi ,  Satoru Sugimoto

IPC分类号： G11C11/34

CPC分类号： G11C16/32 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

摘要： At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (−3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.

摘要翻译： 在读取时，将未选择的字线电压固定为第一预定电压（0V或3V），并且当选择字线时，将所选字线电压设置为第二预定电压（-3.5V或 0 V）。 这种配置消除了在读取时对字线施加脉冲电压，从而可以减小读取干扰的影响。 此外，即使在读取时需要从电源电压到接地电压或电源电压以上的电压的电压，其变为电源电压绝对值的约1.5倍的电压 。 因此，不需要具有大量级的升压电路，结果，能够以低功耗实现缩短的动作时间。

公开(公告)号：US08014199B2

公开(公告)日：2011-09-06

申请号：US11419705

申请日：2006-05-22

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： G11C14/00

CPC分类号： H01L27/11524 ,  G11C11/4045 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/808 ,  H01L29/812

摘要： A memory system is provided forming a switch element having a first side and a second side, forming a cell transistor having a gate terminal, forming a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side, connecting a word line and the memory cell at the first side, connecting a bit line and the memory cell, and connecting a reference source and the memory cell.

摘要翻译： 提供了一种存储系统，其形成具有第一侧和第二侧的开关元件，形成具有栅极端子的单元晶体管，形成具有开关元件和单元晶体管的存储单元，栅极端子连接到第二侧 连接字线和第一侧的存储单元，连接位线和存储单元，以及连接参考源和存储单元。

公开(公告)号：US20110157978A1

公开(公告)日：2011-06-30

申请号：US12976355

申请日：2010-12-22

申请人： Naoharu Shinozaki ,  Masao Taguchi ,  Satoru Sugimoto

发明人： Naoharu Shinozaki ,  Masao Taguchi ,  Satoru Sugimoto

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/32 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

摘要： At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (−3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.

摘要翻译： 在读取时，将未选择的字线电压固定为第一预定电压（0V或3V），并且当选择字线时，将所选字线电压设置为第二预定电压（-3.5V或 0 V）。 这种配置消除了在读取时对字线施加脉冲电压，从而可以减小读取干扰的影响。 此外，即使在读取时需要从电源电压到接地电压或电源电压以上的电压的电压，其变为电源电压绝对值的约1.5倍的电压 。 因此，不需要具有大量级的升压电路，结果，能够以低功耗实现缩短的动作时间。

公开(公告)号：US07724563B2

公开(公告)日：2010-05-25

申请号：US11983864

申请日：2007-11-13

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  H01L27/105

摘要： In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body.

摘要翻译： 在本电阻性存储器阵列中，包括衬底，衬底中的多个源极区域和连接多个源极区域的导体，导体与衬底相邻定位以与多个源极区域形成一个 共同来源。 在一个实施例中，导体是T形横截面的细长金属体。 在另一个实施例中，导体是板状金属体。

公开(公告)号：US20090059652A1

公开(公告)日：2009-03-05

申请号：US12290179

申请日：2008-10-28

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： G11C11/00 ,  H01L47/00

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/24

摘要： In the present method of changing the state of a resistive memory device which is capable of adopting an erased, relatively higher resistance state and a programmed, relatively lower resistance state, the resistive memory device having first and second electrodes and an active layer between the first and second electrodes, an electrical potential is applied across the electrodes and current through the resistive memory device is limited by means of a first current limiting structure to change the resistive memory device from the erased, higher resistance state to the programmed, lower resistance state. Furthermore, an electrical potential is applied across the electrodes and current through the resistive memory device is limited by means of a second current limiting structure to change the resistive memory device from the programmed, lower resistance state to the erased, higher resistance state.

摘要翻译： 在改变能够采用擦除的，相对较高的电阻状态和编程的相对较低的电阻状态的电阻式存储器件的状态的本方法中，电阻式存储器件具有第一和第二电极以及第一和第二电极之间的有源层 和第二电极，跨电极施加电位，并且通过第一电流限制结构来限制通过电阻存储器件的电流，以将阻性存储器件从擦除的较高电阻状态改变为编程的较低电阻状态。 此外，在电极之间施加电势，借助于第二电流限制结构来限制通过电阻性存储器件的电流，以将阻性存储器件从编程的较低电阻状态改变为擦除的较高电阻状态。

公开(公告)号：US20080298115A1

公开(公告)日：2008-12-04

申请号：US11983864

申请日：2007-11-13

申请人： Masao Taguchi

发明人： Masao Taguchi

IPC分类号： G11C11/00 ,  G11C11/36

CPC分类号： H01L27/101 ,  H01L27/105

摘要： In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body.

摘要翻译： 在本电阻性存储器阵列中，包括衬底，衬底中的多个源极区域和连接多个源极区域的导体，导体与衬底相邻定位以与多个源极区域形成一个 共同来源。 在一个实施例中，导体是T形横截面的细长金属体。 在另一个实施例中，导体是板状金属体。

公开(公告)号：US20080014701A1

公开(公告)日：2008-01-17

申请号：US11892872

申请日：2007-08-28

申请人： Kouji Tsunoda ,  Tatsuya Usuki ,  Masao Taguchi

发明人： Kouji Tsunoda ,  Tatsuya Usuki ,  Masao Taguchi

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/0692 ,  H01L29/7883

摘要： A semiconductor device has: an isolation region formed on a semiconductor substrate and defining a continuous active region including a select transistor region and a direct tunnel element region; a gate insulating film formed on a channel region of the select transistor region; a tunnel insulating film formed on a partial area of the direct tunnel element region and having a thickness different from a thickness of the gate insulating film; a continuous floating gate electrode formed above the gate insulating film and the tunnel insulating film; an inter-electrode insulating film formed on a surface of the floating gate electrode; a control gate electrode facing the floating gate electrode via the inter-electrode insulating film; and a pair of source/drain regions formed on both sides of the channel region of the select transistor region and not overlapping the tunnel insulating film.