公开(公告)号：US07187594B2

公开(公告)日：2007-03-06

申请号：US10844563

申请日：2004-05-13

申请人： Akihide Shibata ,  Hiroshi Iwata

发明人： Akihide Shibata ,  Hiroshi Iwata

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C7/1012 ,  G11C7/18 ,  G11C16/04 ,  G11C16/28 ,  G11C2207/002 ,  H01L21/28273 ,  H01L29/7923

摘要： A volatile memory element and a nonvolatile memory element, each of which is constituted of a field effect transistor, are formed on a single semiconductor chip. The volatile memory element includes a body region, a gate electrode, and two diffusion layer regions, and varies an amount of a current, flowing between the diffusion layer regions in applying a voltage to a gate electrode, in accordance with an amount of electric charge retained in the body region. The nonvolatile memory element includes diffusion layer regions, a gate electrode, and two memory function sections, and varies an amount of a current, flowing between the diffusion layer regions in applying a voltage to the gate electrode, in accordance with an amount of electric charge retained in the memory function sections. Thus, it is possible to form the volatile memory and the nonvolatile memory on a single chip with a simple process.

摘要翻译： 在单个半导体芯片上形成由场效应晶体管构成的易失性存储元件和非易失性存储元件。 易失性存储元件包括体区域，栅极电极和两个扩散层区域，并且根据电荷量改变在向栅电极施加电压的扩散层区域之间流动的电流量 保留在身体区域。 非易失性存储元件包括扩散层区域，栅极电极和两个存储器功能部分，并且根据电荷量改变在施加电压至栅电极的扩散层区域之间流动的电流量 保留在记忆功能部分。 因此，可以通过简单的处理在单个芯片上形成易失性存储器和非易失性存储器。

公开(公告)号：US07177188B2

公开(公告)日：2007-02-13

申请号：US10775254

申请日：2004-02-11

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Yoshifumi Yaoi ,  Yasuaki Iwase ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Kenichi Tanaka

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Yoshifumi Yaoi ,  Yasuaki Iwase ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Kenichi Tanaka

IPC分类号： G11C16/00

CPC分类号： H01L21/28273 ,  G11C16/0408 ,  H01L21/28282 ,  H01L29/7923

摘要： A semiconductor memory device includes: a memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; and an amplifier, the memory cell and the amplifier being connected to each other so that an output of the memory cell is inputted to the amplifier.

摘要翻译： 半导体存储器件包括：存储单元，具有通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，设置在沟道区域两侧的扩散区域，并具有相反的导电类型 形成在栅电极的两侧并具有保持电荷的功能的存储器功能单元; 以及放大器，存储单元和放大器彼此连接，使得存储单元的输出被输入到放大器。

公开(公告)号：US20060208312A1

公开(公告)日：2006-09-21

申请号：US11414226

申请日：2006-05-01

申请人： Hiroshi Iwata ,  Takayuki Ogura ,  Akihide Shibata ,  Kouichirou Adachi

发明人： Hiroshi Iwata ,  Takayuki Ogura ,  Akihide Shibata ,  Kouichirou Adachi

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0491 ,  H01L21/28282 ,  H01L21/28291 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the substrate in such a manner as to cover an upper surface and side surfaces of the gate electrode. The device further includes an interlayer insulator formed on and in contact with the coating film. The device still further includes contact members which extend vertically through the interlayer insulator and the coating film on the source/drain diffusion regions and which are electrically connected to the source/drain diffusion regions, respectively. The coating film and the interlayer insulator are made of materials which are selectively etchable to each other. Thus, the issues of overerase and read failures due to the overerase can be solved, and the device reliability can be enhanced.

摘要翻译： 半导体存储装置包括在半导体衬底上具有栅极绝缘体，栅极电极和一对源极/漏极扩散区域的场效应晶体管。 该装置还包括由电介质构成的涂膜，其具有存储电荷的功能，并以覆盖栅电极的上表面和侧表面的方式形成在基板上。 该装置还包括形成在涂膜上并与涂膜接触的层间绝缘体。 该装置还包括分别垂直延伸通过层间绝缘体和源极/漏极扩散区上的涂膜并且分别与源/漏扩散区电连接的接触构件。 涂膜和层间绝缘体由可相互选择性地蚀刻的材料制成。 因此，可以解决由于过度过热导致的过度读取和读取故障的问题，并且可以提高器件的可靠性。

公开(公告)号：US07050337B2

公开(公告)日：2006-05-23

申请号：US10848082

申请日：2004-05-19

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C7/00

CPC分类号： G11C16/24

摘要： A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane. Further, the CPU writes a second byte of data into the second plane and writes the second byte of data having been stored in the second plane while writing the first byte of data having been stored in the first plane into the memory array.

摘要翻译： 一种向非易失性半导体存储装置提供高速写入的写入控制系统，包括：（a）多个存储元件，每个存储元件具有：设置在具有中间栅极绝缘膜的半导体层上的栅电极; 设置在栅电极下方的沟道区; 扩散区，设置在沟道区的两侧，具有与沟道区相反的极性; 以及设置在栅电极两侧的具有保持电荷功能的存储器功能部件，（b）包括页缓冲电路的存储器阵列，（c）CPU控制对存储器阵列的写入。 CPU用第一个数据字节加载页面缓冲电路的第一个平面，并用第一个平面中存储的数据的第一个字节进行写入。 此外，CPU将第二字节的数据写入第二平面，并且将已经存储在第一平面中的数据的第一字节写入存储器阵列中，将已经存储在第二平面中的数据的第二字节写入。

公开(公告)号：US07050331B2

公开(公告)日：2006-05-23

申请号：US10851709

申请日：2004-05-20

申请人： Nobuaki Matsuoka ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

发明人： Nobuaki Matsuoka ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Hiroshi Iwata ,  Akihide Shibata

IPC分类号： G11C16/04

CPC分类号： H01L29/66833 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/16 ,  H01L21/28282 ,  H01L29/7923

摘要： The present invention provides a semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged, a user interface circuit including a command queue having a logic circuit for accepting commands issued by an external user and generating a program memory address, and an array control circuit having a microcontroller and a program memory for storing therein an execution code, and executing an operation on the memory cell array, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.

摘要翻译： 本发明提供了一种半导体存储器件，包括其中布置有多个存储器单元的存储单元阵列，用户接口电路包括具有用于接受由外部用户发出的命令并产生程序存储器地址的逻辑电路的命令队列， 以及阵列控制电路，具有微控制器和程序存储器，用于在其中存储执行代码，并对存储单元阵列执行操作，其中存储单元包括通过栅极绝缘膜形成在半导体层上的栅电极， 设置在栅极电极下方的扩散区域，设置在沟道区域的两侧并具有与沟道区域相反的导电类型的扩散区域，以及形成在栅电极两侧并具有保持电荷功能的存储功能元件。

公开(公告)号：US07038282B2

公开(公告)日：2006-05-02

申请号：US10770627

申请日：2004-02-04

申请人： Kei Tokui ,  Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata ,  Masaru Nawaki

发明人： Kei Tokui ,  Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata ,  Masaru Nawaki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792 ,  H01L29/7923

摘要： A semiconductor storage device includes a voltage supply circuit generating a voltage of 5V, a voltage polarity inversion circuit generating a voltage of −5V, a select-and-connect circuit supplying the voltages of 5V and −5V to a memory cell array, a 5 V voltage level detection circuit detecting the voltage derived from the voltage supply circuit, and a −5 V voltage level detection circuit detecting the voltage derived from the voltage polarity inversion circuit. Absolute values of the voltages detected by the voltage level detection circuits are lower than ever before. This allows a gate insulation film to be thinner. A memory-function film is formed on both sides of a gate electrode in the semiconductor storage device. This also make the gate insulation film thinner. The thin gate insulation film suppresses the short-channel effect, so that each memory element of the memory cell array is miniaturized.

摘要翻译： 半导体存储装置包括产生5V电压的电压供给电路，产生-5V的电压的电压极性反转电路，向存储单元阵列供给5V和-5V的电压的选择和连接电路，5 V电压检测电路，检测从电压供给电路得到的电压;以及-5V电压电平检测电路，检测从电压极性反转电路得到的电压。 由电压电平检测电路检测到的电压的绝对值比以前低。 这允许栅极绝缘膜更薄。 存储功能膜形成在半导体存储装置中的栅电极的两侧。 这也使栅极绝缘膜更薄。 薄栅绝缘膜抑制短沟道效应，使得存储单元阵列的每个存储元件小型化。

公开(公告)号：US20060081941A1

公开(公告)日：2006-04-20

申请号：US11289493

申请日：2005-11-30

申请人： Hiroshi Iwata ,  Akihide Shibata

发明人： Hiroshi Iwata ,  Akihide Shibata

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  B82Y10/00 ,  G11C16/0466 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/118 ,  H01L27/1203 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor storage device having: a first conductivity type region formed in a semiconductor layer; a second conductivity type region formed in the semiconductor layer in contact with the first conductivity type region; a memory functional element disposed on the semiconductor layer across the boundary of the first and second conductivity type regions; and an electrode provided in contact with the memory functional element and on the first conductivity type region via an insulation film, and a portable electronic apparatus comprising the semiconductor storage device. The present invention can fully cope with scale-down and high-integration by constituting a selectable memory cell substantially of one device.

公开(公告)号：US07009884B2

公开(公告)日：2006-03-07

申请号：US10848260

申请日：2004-05-19

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/06

CPC分类号： H01L29/66833 ,  G11C11/5628 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/3454 ,  H01L21/28282 ,  H01L29/792

摘要： A semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements are arranged and a program verify circuit 30. The memory element 1, 33 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on opposite sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies 109 that are located on opposite sides of the gate electrode 104 and have a function of retaining electric charge. A program load register 32 of the program verify circuit 30 eliminates a state that a memory element 33 which has initially been verified as having been correctly programmed needs to be further programmed.

摘要翻译： 半导体存储装置包括其中布置有多个存储元件的存储单元阵列21和程序验证电路30。 存储元件1,33包括通过栅极绝缘体103形成在半导体层102上的栅极电极104，配置在栅电极104下方的沟道区域，位于沟道区域相对侧的扩散区域107a，107b 并且具有与沟道区域相反的导电类型，以及位于栅电极104的相对侧上并具有保持电荷的功能的记忆功能体109。 程序验证电路30的程序加载寄存器32消除了最初被验证为被正确编程的存储元件33需要被进一步编程的状态。

公开(公告)号：US20060044886A1

公开(公告)日：2006-03-02

申请号：US11213927

申请日：2005-08-30

申请人： Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata

发明人： Hiroshi Iwata ,  Yoshifumi Yaoi ,  Akihide Shibata

IPC分类号： G11C5/14

CPC分类号： G11C16/28 ,  G11C7/14

摘要： Characteristic fluctuation of a reference cell due to read disturb is prevented. A memory cell 27m and a reference cell 27r respectively have memory function bodies that are formed on both sides of a gate electrode and have a function to retain electric charge or polarization. The memory cell 27m can store independent information pieces in memory function bodies 27mr and 27ml located on both sides of the gate electrode and the independent information pieces are read therefrom. On the other hand, in the reference cell 27r, only the information piece stored in a memory function body 27rl located on one side of the gate electrode is referred to in a sense amplifier 22.

摘要翻译： 防止由于读取干扰引起的参考单元的特性波动。 存储单元27m和参考单元27r分别具有形成在栅电极的两侧上并具有保持电荷或极化的功能的记忆功能体。 存储单元27m可以将独立的信息块存储在位于栅电极两侧的存储器功能体27mr和27ml中，并从其中读取独立的信息。 另一方面，在参考单元27r中，在读出放大器22中仅参考存储在位于栅电极一侧的存储器功能体27r1中的信息片。

公开(公告)号：US06992933B2

公开(公告)日：2006-01-31

申请号：US10848614

申请日：2004-05-19

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C11/34

CPC分类号： H01L29/66825 ,  G11C11/22 ,  G11C16/0475 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887

摘要： A method of verifying programming of a nonvolatile memory cell to a desired state, the method comprising the steps of: selecting first and second references respectively corresponding to first and second voltages; applying a programming voltage to the memory cell; sensing a threshold voltage level of the memory cell; and comparing the sensed threshold voltage level with the first and second references and, in the case where the threshold voltage level is higher than the first reference and lower than the second reference, indicating that the memory cell is programmed into the desired state, wherein the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region formed below the gate electrode, a source and a drain as diffusion regions formed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

摘要翻译： 一种将非易失性存储单元的编程验证为期望状态的方法，所述方法包括以下步骤：分别对应于第一和第二电压选择第一和第二参考; 将编程电压施加到所述存储器单元; 感测存储器单元的阈值电压电平; 以及将感测的阈值电压电平与第一和第二参考值进行比较，并且在阈值电压电平高于第一参考值且低于第二参考值的情况下，指示存储器单元被编程到期望状态，其中 非易失性存储单元包括通过栅极绝缘膜形成在半导体层上的栅极电极，形成在栅极电极下方的沟道区域，作为在沟道区域的两侧形成的扩散区域的源极和漏极，并且具有与 沟道区域以及形成在栅电极的两侧上并具有保持电荷功能的存储功能单元。