公开(公告)号：US20210391029A1

公开(公告)日：2021-12-16

申请号：US16903066

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Tao Liu ,  Chun Sum Yeung ,  Xiangang Luo

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/52

Abstract: A replacement block pool for a memory device is established. The replacement block pool comprises one or more valid blocks from a set of valid blocks in the memory device determined based on a constraint defining a minimum number of valid blocks for the memory device. A grown bad block is detected in the memory device. The grown bad block is replaced with a replacement block from the replacement block pool in response to detecting the grown bad block.

公开(公告)号：US20210342191A1

公开(公告)日：2021-11-04

申请号：US17234225

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang

IPC: G06F9/50 ,  G06F3/06 ,  G06F12/02 ,  G06F9/30

Abstract: Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.

公开(公告)号：US20210303394A1

公开(公告)日：2021-09-30

申请号：US17228425

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Xiangang Luo ,  Jianmin Huang ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam

IPC: G06F11/10 ,  G11C7/10 ,  G11C11/419 ,  G06F12/02

Abstract: Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.

公开(公告)号：US11106530B2

公开(公告)日：2021-08-31

申请号：US16723836

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Falgun G. Trivedi ,  Harish Reddy Singidi ,  Xiangang Luo ,  Preston Allen Thomson ,  Ting Luo ,  Jianmin Huang

IPC: G06F11/10 ,  G06F12/02 ,  G06F12/0882 ,  G06F11/07

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210175902A1

公开(公告)日：2021-06-10

申请号：US17181712

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Ting Luo

IPC: H03M13/11 ,  G06F11/10

Abstract: Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.

公开(公告)号：US20210096984A1

公开(公告)日：2021-04-01

申请号：US16586519

申请日：2019-09-27

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Qing Liang

IPC: G06F12/02 ,  G06F12/1045 ,  G06F12/0873 ,  G06F12/0804 ,  G06F13/16

Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.

公开(公告)号：US10930352B2

公开(公告)日：2021-02-23

申请号：US16601275

申请日：2019-10-14

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Jung Sheng Hoei ,  Harish Reddy Singidi ,  Ting Luo ,  Ankit Vinod Vashi

IPC: G11C16/10 ,  G11C16/34 ,  G11C7/04

Abstract: Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.

公开(公告)号：US10747612B2

公开(公告)日：2020-08-18

申请号：US16267586

申请日：2019-02-05

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Xiangang Luo ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G06F11/10 ,  G06F11/00 ,  H03M13/00 ,  G06F11/14

Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

公开(公告)号：US20200211603A1

公开(公告)日：2020-07-02

申请号：US16555508

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Patroclo Fumagalli ,  Scott Anthony Stoller ,  Alessandro Magnavacca ,  Andrea Pozzato

IPC: G11C5/14 ,  G06F11/07 ,  G11C11/4099 ,  G11C29/38

Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.

公开(公告)号：US20240411475A1

公开(公告)日：2024-12-12

申请号：US18812356

申请日：2024-08-22

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Xiangang Luo ,  Chun Sum Yeung ,  Kulachet Tanpairoj

IPC: G06F3/06

Abstract: An apparatus can include a block program erase count (PEC) component. The block PEC component can monitor a quantity of program erase counts (PECs) for each particular type of block of a non-volatile memory array. The block PEC component can further determine which block of the superblock to write host data to next based on the quantity of PECs. The block PEC component can further write host data to the determined block.