公开(公告)号：US08227861B2

公开(公告)日：2012-07-24

申请号：US12975808

申请日：2010-12-22

申请人： Hongning Yang ,  Xin Lin ,  Jiang-Kia Zuo

发明人： Hongning Yang ,  Xin Lin ,  Jiang-Kia Zuo

IPC分类号： H01L21/70

CPC分类号： H01L29/66484 ,  H01L29/1041 ,  H01L29/7831 ,  H01L29/7833

摘要： A semiconductor device includes a substrate, a source region formed over the substrate, a drain region formed over the substrate, a first gate electrode over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode over the substrate adjacent to the drain region and between the source and drain regions.

摘要翻译： 半导体器件包括衬底，形成在衬底上的源极区域，形成在衬底上的漏极区域，与衬底相邻的源极区域和源极区域与漏极区域之间的第一栅电极，以及位于源极区域和漏极区域之间的第二栅电极， 衬底，其与漏极区域相邻并且在源极和漏极区域之间。

公开(公告)号：US08212292B2

公开(公告)日：2012-07-03

申请号：US12622625

申请日：2009-11-20

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kia Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kia Zuo

IPC分类号： H01L31/0328

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/7322

摘要： An improved bipolar transistor (40, 40′) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40′) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40′) is much larger than a conventional bipolar transistor (20) made using the same CMOS process. By adjusting the lateral extent (4661) of the transition zone (466), the properties of the improved transistor (40, 40′) can be tailored to suit different applications without modifying the underlying CMOS IC process.

摘要翻译： 提供改进的双极晶体管（40,40'），可通过CMOS IC工艺制造而无需附加步骤。 改进的晶体管（40,40'）包括具有不同深度（4821,4481）的第一（482）和第二（484）部分的发射器（48），位于发射器（48）下方的基座（46）具有中心部分 （462）位于发射器（48）的第一部分（482）下方的第一基底宽度（4623）的外围部分（462），具有大于第一基部宽度（4623）的第二基底宽度（4643）的周边部分（464） 发射器（48）的第二部分（484）和位于第一（462）和第二（464）部分之间的侧向位于第三基部宽度（4644）和横向范围（4661）的过渡区（466） 基部（46）和底部（46）下方的收集器（44）。 晶体管（40,40'）的增益比使用相同CMOS工艺制造的传统双极晶体管（20）大得多。 通过调整过渡区域（466）的横向范围（4661），改进的晶体管（40,40'）的特性可以被调整以适应不同的应用而不修改底层的CMOS IC工艺。

公开(公告)号：US20110320359A1

公开(公告)日：2011-12-29

申请号：US13139773

申请日：2009-06-22

申请人： Dake Li ,  Jinji Zhao ,  Xin Lin ,  Haihui Huang

发明人： Dake Li ,  Jinji Zhao ,  Xin Lin ,  Haihui Huang

IPC分类号： G06Q20/00

CPC分类号： H04L63/12 ,  G06Q20/3829 ,  H04L63/0442

摘要： A secure communication method and device based on application layer for mobile financial service. According to the invention, the exchanged messages in the financial transaction are few, and the requirement for the processing capability of the mobile terminal is low. The invention uses the digital signature technology for information abstract based on asymmetric secret keys, and the integrity of the transaction information is guaranteed and non-repudiation requirement is met. The invention also uses digital envelop technology based on asymmetric secret keys, and the secrecy of the transaction information. The strand space theory proves that the security of the preferred embodiment of the invention can be guaranteed.

摘要翻译： 一种基于移动金融服务应用层的安全通信方式和设备。 根据本发明，金融交易中交换的消息很少，移动终端的处理能力要求低。 本发明使用数字签名技术进行基于非对称密钥的信息抽象，保证交易信息的完整性，满足不可否认性要求。 本发明还使用基于非对称密钥的数字包络技术和交易信息的保密性。 线空间理论证明可以保证本发明的优选实施例的安全性。

公开(公告)号：US5945866A

公开(公告)日：1999-08-31

申请号：US807611

申请日：1997-02-27

申请人： Stephen J. Fonash ,  Xin Lin ,  Anand Krishnan ,  Vyshnavi Suntharalingam

发明人： Stephen J. Fonash ,  Xin Lin ,  Anand Krishnan ,  Vyshnavi Suntharalingam

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G2310/06 ,  G09G2320/0214

摘要： A method for reducing the field dependence of an off-state current flow condition in a field-effect transistor having a source electrode, a drain electrode and a gate electrode, includes the steps of: applying a far off-state bias between the drain electrode and the gate electrode to drive a conduction channel in the field effect transistor into a far off-state; and applying a far off-state bias between the source electrode and the gate electrode to again drive the conduction channel into a far off-state; wherein both applying steps cause application of the far off-state bias for a sufficient time to reduce gate voltage dependency of off-state current flow in the conduction channel during a period when an off-state potential is applied to the gate electrode.

摘要翻译： 一种用于降低具有源电极，漏电极和栅电极的场效应晶体管中的截止电流流动状态的场依赖性的方法包括以下步骤：在漏极之间施加远离状态偏置 以及栅电极，将场效应晶体管的导通通道驱动为远离状态; 以及在所述源电极和所述栅电极之间施加远离状态偏置以再次将所述导通通道驱动到远离状态; 其中两个施加步骤使得在关闭状态电位施加到栅极电极的时段期间施加远离状态偏压足够的时间以减小导通通道中截止态电流的栅极电压依赖性。

公开(公告)号：US09401412B2

公开(公告)日：2016-07-26

申请号：US14804097

申请日：2015-07-20

申请人： Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06 ,  H01L21/3205 ,  H01L21/265 ,  H01L29/08

CPC分类号： H01L29/66121 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/32053 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/6609 ,  H01L29/66128 ,  H01L29/861 ,  H01L29/8611

摘要： An embodiment of a method of fabricating a diode having a plurality of regions of a first conductivity type and a buried region of a second conductivity type includes performing a first dopant implantation procedure to form the buried region, performing a second dopant implantation procedure to form an intermediate region of the plurality of regions, and performing a third dopant implantation procedure to form a contact region of the plurality of regions. The second and third dopant implantation procedures are configured such that the intermediate region is electrically connected with the contact region. The first, second, and third dopant implantation procedures are configured such that the buried region extends laterally across the contact region and the intermediate region to establish first and second junctions of the diode, respectively, and such that the first junction has a lower breakdown voltage than the second junction.

摘要翻译： 制造具有第一导电类型的多个区域和第二导电类型的掩埋区域的二极管的方法的实施例包括执行第一掺杂剂注入步骤以形成掩埋区域，执行第二掺杂剂注入工艺以形成 并且执行第三掺杂剂注入过程以形成所述多个区域的接触区域。 第二和第三掺杂剂注入程序被配置为使得中间区域与接触区域电连接。 第一，第二和第三掺杂剂注入过程被配置为使得掩埋区域横向延伸穿过接触区域和中间区域以分别建立二极管的第一和第二结，并且使得第一结点具有较低的击穿电压 比第二交界处。

公开(公告)号：US20150325674A1

公开(公告)日：2015-11-12

申请号：US14804097

申请日：2015-07-20

申请人： Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L21/3205 ,  H01L21/265

CPC分类号： H01L29/66121 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/32053 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/6609 ,  H01L29/66128 ,  H01L29/861 ,  H01L29/8611

摘要： An embodiment of a method of fabricating a diode having a plurality of regions of a first conductivity type and a buried region of a second conductivity type includes performing a first dopant implantation procedure to form the buried region, performing a second dopant implantation procedure to form an intermediate region of the plurality of regions, and performing a third dopant implantation procedure to form a contact region of the plurality of regions. The second and third dopant implantation procedures are configured such that the intermediate region is electrically connected with the contact region. The first, second, and third dopant implantation procedures are configured such that the buried region extends laterally across the contact region and the intermediate region to establish first and second junctions of the diode, respectively, and such that the first junction has a lower breakdown voltage than the second junction.

摘要翻译： 制造具有第一导电类型的多个区域和第二导电类型的掩埋区域的二极管的方法的实施例包括执行第一掺杂剂注入步骤以形成掩埋区域，执行第二掺杂剂注入工艺以形成 并且执行第三掺杂剂注入过程以形成所述多个区域的接触区域。 第二和第三掺杂剂注入程序被配置为使得中间区域与接触区域电连接。 第一，第二和第三掺杂剂注入过程被配置为使得掩埋区域横向延伸穿过接触区域和中间区域以分别建立二极管的第一和第二结，并且使得第一结点具有较低的击穿电压 比第二交界处。

公开(公告)号：US20150270333A1

公开(公告)日：2015-09-24

申请号：US14218330

申请日：2014-03-18

申请人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L29/06 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/36

CPC分类号： H01L29/063 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1087 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type.

摘要翻译： 一种器件包括半导体衬底，设置在半导体衬底中并具有第一导电类型的源极和漏极区域，设置在半导体衬底中的体区，具有第二导电类型，并且其中设置源极区，漂移区 设置在具有第一导电类型的半导体衬底中，并且在施加源极和漏极区域之间的偏置电压时，电荷载体在工作期间漂移，设置在半导体衬底中并横向围绕身体区域的器件隔离区域和 漂移区域和设置在器件隔离区域和体区之间并具有第一导电类型的击穿保护区域。

公开(公告)号：US09054149B2

公开(公告)日：2015-06-09

申请号：US13605214

申请日：2012-09-06

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiangkai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiangkai Zuo

IPC分类号： H01L29/73 ,  H01L29/66 ,  H01L21/225

CPC分类号： H01L29/73 ,  H01L21/2253 ,  H01L29/6625

摘要： A method of fabricating a bipolar transistor including emitter and base regions having first and second conductivity types, respectively, includes forming an isolation region at a surface of a semiconductor substrate, the isolation region having an edge that defines a boundary of an active area of the emitter region, and implanting dopant of the second conductivity type through a mask opening to form the base region in the semiconductor substrate. The mask opening spans the edge of the isolation region such that an extent to which the dopant passes through the isolation region varies laterally to establish a variable depth contour of the base region.

摘要翻译： 包括分别具有第一和第二导电类型的发射极和基极区域的双极晶体管的制造方法包括在半导体衬底的表面形成隔离区域，该隔离区域具有界定边界的有源区域 发射极区域和通过掩模开口注入第二导电类型的掺杂剂，以在半导体衬底中形成基极区域。 掩模开口跨越隔离区域的边缘，使得掺杂剂通过隔离区域的程度横向变化，以建立基极区域的可变深度轮廓。

公开(公告)号：US20150123236A1

公开(公告)日：2015-05-07

申请号：US14072151

申请日：2013-11-05

申请人： Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

IPC分类号： H01L29/861 ,  H01L21/265 ,  H01L29/66

CPC分类号： H01L29/66121 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/32053 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/6609 ,  H01L29/66128 ,  H01L29/861 ,  H01L29/8611

摘要： An embodiment of a diode includes a semiconductor substrate, a first contact region having a first conductivity type, a second contact region laterally spaced from the first contact region, and having a second conductivity type, an intermediate region disposed in the semiconductor substrate between the first and second contact regions, electrically connected with the first contact region, and having the first conductivity type, and a buried region disposed in the semiconductor substrate, having the second conductivity type, and electrically connected with the second contact region. The buried region extends laterally across the first contact region and the intermediate region to establish first and second junctions, respectively. The first junction has a lower breakdown voltage than the second junction.

摘要翻译： 二极管的实施例包括半导体衬底，具有第一导电类型的第一接触区域，与第一接触区域横向隔开的第二接触区域，并具有第二导电类型，设置在半导体衬底中的第一接触区域之间的第一接触区域 以及与第一接触区域电连接并且具有第一导电类型的第二接触区域和设置在半导体衬底中的具有第二导电类型并与第二接触区域电连接的掩埋区域。 掩埋区域横向延伸穿过第一接触区域和中间区域以分别建立第一和第二接合点。 第一结具有比第二结低的击穿电压。

公开(公告)号：US09018673B2

公开(公告)日：2015-04-28

申请号：US13601831

申请日：2012-08-31

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/66 ,  H01L29/866 ,  H01L29/06

CPC分类号： H01L29/866 ,  H01L29/0692

摘要： A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.

摘要翻译： 在一个实施例中，公开的齐纳二极管包括形成浅亚表面纬向齐纳结的阳极区域和阴极区域。 齐纳二极管还可以包括将阳极区域与位于远离齐纳结区域的触点和覆盖阳极区域的硅化物阻挡结构互连的阳极接触区域。 齐纳二极管还可以包括在阴极区域和相邻区域的侧边缘之间的接合处的一个或多个浅的子表面纵向p-n结。 相邻区域可以是诸如阳极接触区域的重掺杂区域。 在其他实施例中，齐纳二极管可以包括击穿电压升压区域，其包括位于阴极区域和阳极接触区域之间的较轻掺杂区域。