公开(公告)号：US5945866A

公开(公告)日：1999-08-31

申请号：US807611

申请日：1997-02-27

申请人： Stephen J. Fonash ,  Xin Lin ,  Anand Krishnan ,  Vyshnavi Suntharalingam

发明人： Stephen J. Fonash ,  Xin Lin ,  Anand Krishnan ,  Vyshnavi Suntharalingam

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G2310/06 ,  G09G2320/0214

摘要： A method for reducing the field dependence of an off-state current flow condition in a field-effect transistor having a source electrode, a drain electrode and a gate electrode, includes the steps of: applying a far off-state bias between the drain electrode and the gate electrode to drive a conduction channel in the field effect transistor into a far off-state; and applying a far off-state bias between the source electrode and the gate electrode to again drive the conduction channel into a far off-state; wherein both applying steps cause application of the far off-state bias for a sufficient time to reduce gate voltage dependency of off-state current flow in the conduction channel during a period when an off-state potential is applied to the gate electrode.

摘要翻译： 一种用于降低具有源电极，漏电极和栅电极的场效应晶体管中的截止电流流动状态的场依赖性的方法包括以下步骤：在漏极之间施加远离状态偏置 以及栅电极，将场效应晶体管的导通通道驱动为远离状态; 以及在所述源电极和所述栅电极之间施加远离状态偏置以再次将所述导通通道驱动到远离状态; 其中两个施加步骤使得在关闭状态电位施加到栅极电极的时段期间施加远离状态偏压足够的时间以减小导通通道中截止态电流的栅极电压依赖性。

公开(公告)号：US06531193B2

公开(公告)日：2003-03-11

申请号：US09734232

申请日：2000-12-11

申请人： Stephen J. Fonash ,  Xin Lin ,  Douglas M. Reber

发明人： Stephen J. Fonash ,  Xin Lin ,  Douglas M. Reber

IPC分类号： C23C1640

CPC分类号： H01L21/02164 ,  C23C16/402 ,  C23C16/5096 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/31612

摘要： Silicon dioxide thin film have been deposited at temperatures from 25° C. to 250° C. by plasma enhanced chemical vapor deposition (PECVD) using tetramethylsilane (TMS) as the silicon containing precursor. At these temperatures, the PETMS oxide films have been found to exhibit adjustable stress and adjustable conformality. Post deposition annealing in forming gas at or below the deposition temperatures has been shown to be very effective in improving the PETMS oxide properties while preserving the low temperature aspect of the PETMS oxides.

摘要翻译： 通过使用四甲基硅烷（TMS）作为含硅前体的等离子体增强化学气相沉积（PECVD），在25℃至250℃的温度下沉积二氧化硅薄膜。 在这些温度下，已经发现PETMS氧化物膜具有可调节的应力和可调整的共形性。 已经表明，在沉积温度或低于沉积温度的成形气体中的后沉积退火在改善PETMS氧化物性能同时保持PETMS氧化物的低温方面是非常有效的。

公开(公告)号：US09899500B2

公开(公告)日：2018-02-20

申请号：US14269825

申请日：2014-05-05

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/66 ,  H01L29/872 ,  H01L29/10 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/66893 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/1066 ,  H01L29/107 ,  H01L29/66143 ,  H01L29/872

摘要： A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.

公开(公告)号：US09543379B2

公开(公告)日：2017-01-10

申请号：US14218330

申请日：2014-03-18

申请人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/36 ,  H01L21/8234 ,  H01L27/12

CPC分类号： H01L29/063 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1087 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type.

摘要翻译： 一种器件包括半导体衬底，设置在半导体衬底中并具有第一导电类型的源极和漏极区域，设置在半导体衬底中的体区，具有第二导电类型，并且其中设置源极区，漂移区 设置在具有第一导电类型的半导体衬底中，并且在施加源极和漏极区域之间的偏置电压时，电荷载体在工作期间漂移，设置在半导体衬底中并横向围绕身体区域的器件隔离区域和 漂移区域和设置在器件隔离区域和体区之间并具有第一导电类型的击穿保护区域。

公开(公告)号：US20160025745A1

公开(公告)日：2016-01-28

申请号：US14814238

申请日：2015-07-30

申请人： Jia Guo ,  Xin Lin ,  Steve Georas ,  Patricia Sime

发明人： Jia Guo ,  Xin Lin ,  Steve Georas ,  Patricia Sime

IPC分类号： G01N33/68 ,  A61K38/44 ,  A61K31/713 ,  C12Q1/68

CPC分类号： G01N33/6875 ,  A61K31/7088 ,  A61K31/713 ,  A61K38/44 ,  A61K39/395 ,  A61K39/39533 ,  A61K39/39583 ,  A61K45/00 ,  C12Q1/6883 ,  C12Q2600/106 ,  C12Q2600/112 ,  C12Q2600/136 ,  C12Q2600/154 ,  C12Q2600/158 ,  C12Y114/11027 ,  G01N2800/10 ,  G01N2800/52

摘要： The present invention is directed to methods of diagnosing and treating a fibrotic condition in a mammalian subject. These methods involve measuring the levels of trimethylation at lysine residue 27 of histone-3 and/or measuring the expression levels of EZH2 or YY-1. Agents useful for treating fibrosis or a fibrotic condition are also disclosed.

摘要翻译： 本发明涉及在哺乳动物受试者中诊断和治疗纤维化病症的方法。 这些方法包括测量组蛋白-3的赖氨酸残基27处的三甲基化水平和/或测量EZH2或YY-1的表达水平。 还公开了可用于治疗纤维化或纤维化病症的药剂。

公开(公告)号：US20150380513A1

公开(公告)日：2015-12-31

申请号：US14844608

申请日：2015-09-03

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L21/762 ,  H01L29/10 ,  H01L21/266 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/6625 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/735

摘要： A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity type to form emitter and collector regions laterally spaced from one another in a semiconductor substrate, and performing a second plurality of implantation procedures to implant dopant of a second conductivity type in the semiconductor substrate to form a composite base region. The composite base region includes a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.

摘要翻译： 一种制造双极晶体管器件的方法包括：执行第一多个注入步骤以注入第一导电类型的掺杂剂，以形成在半导体衬底中彼此横向隔开的发射极和集电极区，以及执行第二多个植入步骤以植入 半导体衬底中的第二导电类型的掺杂剂以形成复合基极区域。 复合基极区域包括基极接触区域，在工作期间形成发射极和集电极区域之间的掩埋传导路径的掩埋区域和电连接基极接触区域和掩埋区域的基极连接区域。 基极区域的掺杂剂浓度水平高于掩埋区域，并且横向设置在发射极和集电极区域之间。

公开(公告)号：US09202887B2

公开(公告)日：2015-12-01

申请号：US14466042

申请日：2014-08-22

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

IPC分类号： H01L29/66 ,  H01L29/73 ,  H01L29/735 ,  H01L29/08 ,  H01L21/74

CPC分类号： H01L29/6625 ,  H01L21/74 ,  H01L29/0821 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

摘要： Bipolar transistors and methods for fabricating bipolar transistors are provided. In one embodiment, the method includes the step or process of providing a substrate having therein a semiconductor base region of a first conductivity type and first doping density proximate an upper substrate surface. A multilevel collector structure of a second opposite conductivity type is formed in the base region. The multilevel collector includes a first collector part extending to a collector contact, a second collector part Ohmically coupled to the first collector part underlying the upper substrate surface by a first depth, a third collector part laterally spaced apart from the second collector part and underlying the upper substrate surface by a second depth and having a first vertical thickness, and a fourth collector part Ohmically coupling the second and third collector parts and having a second vertical thickness different than the first vertical thickness.

摘要翻译： 提供双极晶体管和制造双极晶体管的方法。 在一个实施例中，该方法包括提供其中具有第一导电类型的半导体基区和靠近上衬底表面的第一掺杂密度的衬底的步骤或工艺。 第二相反导电类型的多电平集电器结构形成在基极区域中。 所述多级集电器包括延伸到集电极触点的第一集电器部分，第二集电器部分，所述第二集电器部分以欧姆方式耦合到所述上基板表面下方的第一集电器部分第一深度;第三集电器部分，其与所述第二集电器部分横向间隔开， 上部衬底表面具有第二深度并具有第一垂直厚度;以及第四集电器部分，其将所述第二和第三集电器部分欧姆耦合并且具有不同于所述第一垂直厚度的第二垂直厚度。

公开(公告)号：US09184257B2

公开(公告)日：2015-11-10

申请号：US14575204

申请日：2014-12-18

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

IPC分类号： H01L29/735 ,  H01L29/66 ,  H01L29/73 ,  H01L29/732 ,  H01L21/265 ,  H01L29/36 ,  H01L29/06

CPC分类号： H01L29/6625 ,  H01L21/265 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735

摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region.

摘要翻译： 提供半导体器件结构和相关的制造方法。 示例性的半导体器件结构包括具有第一导电类型的半导体材料的集电极区域，在集电极区域内的半导体材料的基极区域，具有与第一导电类型相反的第二导电类型的基极区域和半导体材料的掺杂区域 具有第二导电类型，其中所述掺杂区域电连接到所述基极区域，并且所述集电极区域位于所述基极区域和所述掺杂区域之间。 在示例性实施例中，掺杂区域的掺杂剂浓度大于集电极区域的掺杂剂浓度以消耗集电极区域，因为基极区域的电位超过集电极区域的电位。

公开(公告)号：US09130006B2

公开(公告)日：2015-09-08

申请号：US14047222

申请日：2013-10-07

申请人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Daniel J. Blomberg ,  Jiang-Kai Zuo

IPC分类号： H02H9/04 ,  H01L21/331 ,  H01L29/73 ,  H01L29/735 ,  H01L29/66

CPC分类号： H01L29/6625 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/735

摘要： A device includes a semiconductor substrate, emitter and collector regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite base region disposed in the semiconductor substrate, having a second conductivity type, and including a base contact region, a buried region through which a buried conduction path between the emitter and collector regions is formed during operation, and a base link region electrically connecting the base contact region and the buried region. The base link region has a dopant concentration level higher than the buried region and is disposed laterally between the emitter and collector regions.

摘要翻译： 一种器件包括设置在半导体衬底中的半导体衬底，发射极和集电极区域，具有第一导电类型并且彼此横向间隔开;以及复合衬底区域，设置在半导体衬底中，具有第二导电类型，并且包括 基极接触区域，在工作期间形成发射极和集电极区域之间的掩埋传导路径的埋入区域和电连接基极接触区域和埋入区域的基极连接区域。 基极区域的掺杂剂浓度水平高于掩埋区域，并且横向设置在发射极和集电极区域之间。

公开(公告)号：US20150228713A1

公开(公告)日：2015-08-13

申请号：US14697195

申请日：2015-04-27

申请人： Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Hongning Yang ,  Jiang-Kai Zuo

IPC分类号： H01L29/06 ,  H01L29/861 ,  H01L27/12

CPC分类号： H01L29/063 ,  H01L27/1207 ,  H01L29/0692 ,  H01L29/66204 ,  H01L29/861

摘要： A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a non-uniform cathode region (104) and peripheral anode regions (106, 107) which define vertical and horizontal p-n junctions under the anode contact regions (130, 132), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region (132).

摘要翻译： 提供了沟槽隔离的RESURF二极管结构（100），其包括衬底（150），其中形成阳极（130,132）和阴极（131）接触区域，所述接触区域由浅沟槽隔离区域（114,115） ）以及在阳极接触区域（130,132）下限定垂直和水平pn结的不均匀阴极区（104）和外围阳极区（106,107），其包括被屏蔽的水平阴极/阳极结 通过重掺杂的阳极接触区域（132）。