公开(公告)号：US07298028B2

公开(公告)日：2007-11-20

申请号：US11257593

申请日：2005-10-24

申请人： Chih-Hsiung Lin ,  Nai-Shung Chang

发明人： Chih-Hsiung Lin ,  Nai-Shung Chang

IPC分类号： H01L23/495

CPC分类号： H05K1/0209 ,  H01L23/367 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10734

摘要： A printed circuit board (PCB) for a package substrate of a multi-package module (MPM). The PCB comprises a substrate and a heat sink thereon. The heat sink comprises a first portion under the package substrate of the MPM. The heat sink further comprises a second portion adjacent to the first portion, comprising at least one fin.

摘要翻译： 一种用于多封装模块（MPM）的封装基板的印刷电路板（PCB）。 PCB包括衬底和其上的散热器。 散热器包括在MPM的封装衬底下方的第一部分。 散热器还包括邻近第一部分的第二部分，包括至少一个散热片。

公开(公告)号：US06745275B2

公开(公告)日：2004-06-01

申请号：US09756073

申请日：2001-01-08

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F1314

CPC分类号： G11C5/06 ,  G06F1/26 ,  G11C5/04 ,  G11C8/06 ,  G11C8/12 ,  H05K1/0246 ,  H05K1/0262 ,  H05K1/14 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022 ,  H05K2201/10159

摘要： A feedback system capable of accommodating different memory module loading. The feedback system utilizes the signal received by the data strobe feedback pin of a control chipset to simulate or to obtain memory module loading information so that timing of the data signal and data strobe signal can be adjusted accordingly. Therefore, data can be accurately written to or read from the memory module. The embodiment of this invention includes using a variable reference voltage source and a comparator to adjust the timing of the signal to the data strobe feedback pin, using independent simulating loads circuit and specially designed memory module with simulating load, and using a data strobe signal circuit that includes complete memory module loading.

摘要翻译： 一种能够适应不同存储器模块负载的反馈系统。 反馈系统利用由控制芯片组的数据选通反馈引脚接收的信号来模拟或获得存储器模块负载信息，从而可以相应地调整数据信号和数据选通信号的定时。 因此，可以将数据准确地写入或从存储器模块读取。 本发明的实施例包括使用可变参考电压源和比较器，使用独立的模拟负载电路和专门设计的具有模拟负载的存储器模块来调整信号到数据选通反馈引脚的定时，并使用数据选通信号电路 包括完整的内存模块加载。

公开(公告)号：US06563338B2

公开(公告)日：2003-05-13

申请号：US09921950

申请日：2001-08-03

申请人： Ching-Fu Chuang ,  Nai-Shung Chang

发明人： Ching-Fu Chuang ,  Nai-Shung Chang

IPC分类号： H03K1716

CPC分类号： H03K19/01721 ,  H03K19/0016

摘要： A control circuit, a chipset and a method capable of saving the terminal resistors on a motherboard. Through the determination of connection of a pull-up enable line to a first voltage source Vdd via a resistor, an equivalent resistance is set between the source terminal and the drain terminal of a field effect transistor. The equivalent resistance is almost identical to the terminal resistor and hence can replace the resistor on the motherboard. When the pull-up enable line is connected to the first voltage source Vdd via a resistor, an equivalent resistance of about 45-60&OHgr; is established between the source and drain terminal of the field effect transistor. The equivalent resistance is connected in parallel with an input/output pad and a second voltage source Vtt to replace the original externally connected terminal resistor rt2 at the other end of the bus. If the pull-up enable line is not connected to a first voltage source Vdd via a resistor, the field effect transistor is cut off and an infinite equivalent resistance is created between the source and the drain terminal. The infinite resistance is connected in parallel between the input/output pad and the second voltage source Vtt. The infinite equivalent resistance has little effect on any externally connected terminal resistor rt2 at the other end of the bus. Hence, through enabling or disabling the pull-up enable line, manufacturers are free to choose whether to save output power to the terminal resistor rt2 at the other end of the bus or not.

摘要翻译： 一种控制电路，芯片组和能够在主板上保存终端电阻的方法。 通过经由电阻器确定上拉使能线与第一电压源Vdd的连接，在场效应晶体管的源极端子和漏极端子之间设置等效电阻。 等效电阻几乎与端子电阻相同，因此可以替代主板上的电阻。 当上拉使能线通过电阻连接到第一电压源Vdd时，在场效应晶体管的源极和漏极端之间建立约45-60OMEGA的等效电阻。 等效电阻与输入/输出焊盘和第二电压源Vtt并联连接，以替代总线另一端的原始外部连接的端子电阻器rt2。 如果上拉使能线路没有通过电阻器连接到第一电压源Vdd，则场效应晶体管被切断，并且在源极和漏极端子之间产生无限等效电阻。 无限电阻在输入/输出焊盘和第二电压源Vtt之间并联连接。 无限等效电阻对总线另一端的任何外部连接的端子电阻rt2几乎没有影响。 因此，通过启用或禁用上拉使能线，制造商可以自由选择是否将总线的另一端的终端电阻rt2的输出功率节省。

公开(公告)号：US06484281B1

公开(公告)日：2002-11-19

申请号：US09459763

申请日：1999-12-13

申请人： Hsuan-Yi Wang ,  Jiin Lai ,  Nai-Shung Chang

发明人： Hsuan-Yi Wang ,  Jiin Lai ,  Nai-Shung Chang

IPC分类号： G01R3128

CPC分类号： G01R31/318342

摘要： A software-based simulation system is provided, which can provide the combined functionality of a South Bridge test module and a North Bridge test module based solely on either one of the two modules, i.e., either the South Bridge test module or the North Bridge test module without having to use both. This software-based simulation system is characterized in the use of a PCI master modeling circuit and a PCI slave modeling circuit which are capable of simulating the functionality of the North Bridge chipset in the case that only the South Bridge chipset and no North Bridge chipset is included in the simulation system, and are further capable of simulating the functionality of the South Bridge chipset in the case that only the North Bridge chipset and no South Bridge chipset is included in the simulation system.

摘要翻译： 提供了一个基于软件的仿真系统，可以提供南桥测试模块和北桥测试模块的组合功能，该模块仅基于两个模块之一，即南桥测试模块或北桥测试 模块，而不必使用两者。 该基于软件的仿真系统的特征在于使用PCI主建模电路和PCI从属建模电路，其能够模拟北桥芯片组的功能，仅在南桥芯片组和北桥芯片组为 包括在仿真系统中，并且在模拟系统中仅包括北桥芯片组且没有南桥芯片组的情况下，还能够模拟南桥芯片组的功能。

公开(公告)号：US06424555B1

公开(公告)日：2002-07-23

申请号：US09672919

申请日：2000-09-28

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G11C506

CPC分类号： G11C5/04

摘要： A mother board and a computer system capable of flexibly using the SDRAM and the DDRAM. The mother board has several memory module slots, a voltage comparator, a clock generator and a chip set. Each of the memory module slots comprises a reference voltage pin, and the reference voltage pins of the memory module slots are connected to each other in parallel. The voltage comparator is coupled to the reference voltage pins of the memory module slots to detect whether the voltage at the reference voltage pin is equivalent to a reference voltage. The clock generator is coupled to an output of the voltage comparator. When the voltage at the reference voltage pin is equal to the reference voltage, a differential clock signal is generated, and when the votlage is different from the reference voltage, a normal clock signal is generated. The chip set is coupled to the output of the voltage comparator. When the voltage is equal to the reference voltage, the chip set is operated under a double data rate mode. If the voltage is different from the reference voltage, the chip set is operated under a normal data rate mode.

摘要翻译： 主板和能够灵活使用SDRAM和DDRAM的计算机系统。 母板具有多个存储器模块插槽，电压比较器，时钟发生器和芯片组。 每个存储器模块插槽包括参考电压引脚，并且存储器模块插槽的参考电压引脚彼此并联连接。 电压比较器耦合到存储器模块插槽的参考电压引脚，以检测参考电压引脚上的电压是否等于参考电压。 时钟发生器耦合到电压比较器的输出。 当参考电压引脚上的电压等于参考电压时，产生差分时钟信号，并且当电压与参考电压不同时，产生正常的时钟信号。 芯片组耦合到电压比较器的输出端。 当电压等于参考电压时，芯片组在双数据速率模式下运行。 如果电压与参考电压不同，则芯片组以正常数据速率模式运行。

公开(公告)号：US06415407B1

公开(公告)日：2002-07-02

申请号：US09306113

申请日：1999-05-06

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F1100

CPC分类号： G06F11/273

摘要： A debugging device is provided for use in a system controller chip on a computer motherboard, such as a Pentium-based computer motherboard, to facilitate a debugging procedure on the system controller chip whenever a malfunction occurs to the system controller chip. Consequently, internal signals of the chip are correctly connected to chip leads. Under normal operating conditions of the system controller chip, the debugging device connects the connecting-pad area to the control unit and disconnects the connecting-pad the control unit and connects the connecting-pad area successively in a predetermined sequence to the function blocks, allowing the function blocks to undergo an on-site debugging procedure one by one. The debugging device allows an on-site debugging procedure on the system controller chip in real time, and also allows the system controller chip to undergo a benchmark test to check for the reliability in the overall functionality of the system controller chip.

摘要翻译： 提供了一种用于计算机主板上的系统控制器芯片（例如基于奔腾的计算机主板）的调试装置，以便在系统控制器芯片出现故障时便于系统控制器芯片上的调试过程。 因此，芯片的内部信号正确连接到芯片引线。 在系统控制器芯片的正常工作条件下，调试设备将连接区域连接到控制单元，并将控制单元断开连接板，并按照预定顺序将连接板区域连接到功能块，允许 功能块逐个进行现场调试。 调试设备允许实时在系统控制器芯片上进行现场调试程序，还允许系统控制器芯片进行基准测试，以检查系统控制器芯片的整体功能的可靠性。

公开(公告)号：US06405288B1

公开(公告)日：2002-06-11

申请号：US09371700

申请日：1999-08-10

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F1300

CPC分类号： G06F12/0804

摘要： A memory access control method and system is provided for use on a computer system to control the memory access operation by a central processing unit (CPU) to a memory unit in a more efficient manner. This memory access control method and system is characterized in the capability of switching the memory access operation between a waiting mode and a non-waiting mode based on the current L1 write-back condition of the read requests from the CPU. In the waiting mode, the memory unit responds to each read request in such a manner as to wait until the L1 write-back signal of the read request is issued and then either perform a read operation for the current read request if the L1 write-back signal indicates a cache miss, or perform a cache write-back operation if the L1 write-back signal indicates a cache hit. In the non-waiting mode, the memory unit responds to each read request in such a manner that it will always promptly perform a read operation for the current read request without waiting until the CPU issues the L1 write-back signal of the current read request, and in the event that the subsequently received L1 write-back signal of the read request indicates a cache hit, promptly abandon the currently retrieved data from the memory unit and then performing a cache write-back operation.

摘要翻译： 提供了一种在计算机系统上使用的存储器访问控制方法和系统，以更有效的方式将中央处理单元（CPU）的存储器访问操作控制到存储器单元。 该存储器访问控制方法和系统的特征在于，基于来自CPU的读取请求的当前L1回写条件，能够在等待模式和不等待模式之间切换存储​​器访问操作。 在等待模式下，存储器单元以这样的方式响应于每个读取请求，直到发出读取请求的L1写回信号，然后如果L1写入请求执行对当前读取请求的读取操作， 返回信号指示高速缓存未命中，或者如果L1回写信号指示高速缓存命中，则执行高速缓存回写操作。 在非等待模式中，存储器单元以这样的方式响应于每个读取请求，使得它将始终对当前读取请求执行读取操作，而不等待CPU发出当前读取请求的L1回写信号 并且在随后接收到的读取请求的L1回写信号指示高速缓存命中的情况下，迅速地从存储器单元放弃当前检索的数据，然后执行高速缓存回写操作。

公开(公告)号：US06404610B1

公开(公告)日：2002-06-11

申请号：US09667926

申请日：2000-09-22

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： H02H500

CPC分类号： G06F1/206

摘要： A temperature sensing system for monitoring and controlling temperatures of various peripheral devices inside a notebook type of computer. The temperature sensing system uses thermistor as temperature sensor. The thermistor is positioned around a peripheral device and formed a potential divider circuit with another resistor. Next, the voltage produced by the divider circuit is fed to a voltage detection pin of a chipset. Inside the chipset, the divider voltage can be compared with a reference so that appropriate action can be taken to cool down particular peripheral device. In addition, the temperature sensor of this invention can be placed anywhere inside a notebook computer including the area surrounding the peripheral device or even inside the peripheral device. Moreover, no additional control chips for operating those temperature sensors are needed, and hence production cost can be lowered.

摘要翻译： 一种温度感测系统，用于监测和控制笔记本计算机内各种外围设备的温度。 温度传感系统使用热敏电阻作为温度传感器。 热敏电阻位于外围设备周围，并与另一个电阻器形成分压电路。 接下来，由分频器电路产生的电压被馈送到芯片组的电压检测引脚。 在芯片组内部，可以将分压器电压与参考值进行比较，以便采取适当的措施冷却特定的外围器件。 此外，本发明的温度传感器可以放置在包括围绕外围设备的区域或甚至外围设备内的笔记本计算机内的任何地方。 此外，不需要用于操作这些温度传感器的附加控制芯片，因此可以降低生产成本。

公开(公告)号：US06397266B1

公开(公告)日：2002-05-28

申请号：US09235640

申请日：1999-01-22

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F1300

CPC分类号： G06F13/4226

摘要： An input/output control device used to enhance the efficiency of accesses to input/output devices in a computer system is provided. The input/output control device includes a means for storing a mapping table containing pairs of address and response time data associated with the input/output control devices, respectively. When a central processing unit (CPU) accesses an input/output device, a ready signal RDY or a defer signal DEFER is transmitted to the central processing unit from the input/output control device according to a response time corresponding to the accessed input/output device. Thus, the standby time of the central processing unit is greatly reduced, resulting in a better efficiency for the entire computer system.

摘要翻译： 提供了一种用于提高对计算机系统中输入/输出设备的访问效率的输入/输出控制装置。 输入/输出控制装置包括用于分别存储与输入/输出控制装置相关联的地址和响应时间数据对的映射表的装置。 当中央处理单元（CPU）访问输入/输出设备时，根据对应于所访问的输入/输出的响应时间，从输入/输出控制设备向中央处理单元发送就绪信号RDY或延迟信号DEFER 设备。 因此，中央处理单元的待机时间大大降低，导致整个计算机系统的更好的效率。

公开(公告)号：US06378055B1

公开(公告)日：2002-04-23

申请号：US09359450

申请日：1999-07-22

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F1208

CPC分类号： G06F12/0804 ,  G06F13/161

摘要： A memory accessing and controlling unit that controls the transfer of data between a CPU and a memory cluster. The memory accessing and controlling unit comprises a CPU interface circuit and a memory controlling circuit. When the CPU interface circuit picks up a data read request signal from the CPU, a corresponding internal data read request is forwarded to the memory controlling circuit. Next, the memory controlling circuit is sent out some controlling instructions to the memory cluster for reading out the requested data to the CPU. If the CPU also sends out an L1 write-back signal some time later, the memory controlling circuit immediately terminates the current reading operation so that data from the CPU can be written back to the memory cluster.

摘要翻译： 一个存储器访问和控制单元，用于控制CPU和存储器集群之间的数据传输。 存储器访问和控制单元包括CPU接口电路和存储器控制电路。 当CPU接口电路从CPU中取出数据读取请求信号时，相应的内部数据读取请求被转发到存储器控制电路。 接下来，将存储器控制电路发送到存储器簇的一些控制指令，以将所请求的数据读出到CPU。 如果CPU在一段时间后还发出一个L1回写信号，则存储器控制电路立即终止当前的读取操作，使得来自CPU的数据可以被写回到存储器簇。