公开(公告)号：US06627512B2

公开(公告)日：2003-09-30

申请号：US10090607

申请日：2002-03-06

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

IPC分类号： H01L2176

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L27/1203

摘要： In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

公开(公告)号：US06495898B1

公开(公告)日：2002-12-17

申请号：US09639953

申请日：2000-08-17

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto

IPC分类号： H01L2900

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L27/1203

摘要： In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

摘要翻译： 在组合隔离氧化膜（BT1）中，靠近栅电极（GT13）的部分通过SOI层（3）到达埋入氧化膜（2），而靠近另一栅电极（GT12）的部分具有截面形状 在其下部设置有井区。 组合隔离氧化膜（BT1）的边缘部分的形状在LOCOS隔离氧化膜中呈鸟喙的形式。 因此，限定栅极氧化膜（GO12，GO13）的边缘部分的部分的厚度局部增加。 这样提供了一种半导体器件及其制造方法，该半导体器件包括具有防止绝缘击穿而不增加其厚度的栅极氧化膜的MOS晶体管。

公开(公告)号：US06461935B2

公开(公告)日：2002-10-08

申请号：US09989152

申请日：2001-11-21

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor device having a trench-shaped isolator, adjacent to the semiconductor element region is formed having a width which is continuously decreased in the downward direction for relaxing the stress in the silicon layer. Embodiments include forming a patterned dielectric layer on an SOI substrate, forming sidewall spacers thereon, and etching the underlying silicon layer followed by oxidation or controlled etching to form the trench with downwardly decreasing side surfaces.

摘要翻译： 具有与半导体元件区域相邻的沟槽形隔离器的半导体器件形成为具有在向下方向上连续减小的宽度，以缓解硅层中的应力。 实施例包括在SOI衬底上形成图案化的电介质层，在其上形成侧壁间隔物，并蚀刻下面的硅层，接着进行氧化或受控蚀刻，以形成具有向下减少的侧表面的沟槽。

公开(公告)号：US06372599B1

公开(公告)日：2002-04-16

申请号：US09371027

申请日：1999-08-10

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： The invention provides a semiconductor device having the trench-shaped isolator is provided with a portion which is adjacent to the semiconductor element region, of which the width is continuously decreased in the downward direction, and of which the surface is planarized near the semiconductor element region, for relaxing the stress in the silicon layer and being flat the surface of the trench-shaped insulator, and method of manufacturing the same.

公开(公告)号：US5841171A

公开(公告)日：1998-11-24

申请号：US746951

申请日：1996-11-18

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Yasuo Inoue

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78654

摘要： In forming an element isolating region in a silicon semiconductor layer of an SOI substrate, a silicon nitride film of a predetermined thickness is deposited over an oxide film formed on a SOI layer. The silicon nitride film is patterned in a design size of active regions, and side walls of a silicon nitride film are formed on the side surfaces of the patterned silicon nitride film. A first LOCOS process is carried out using the nitride film as an oxidation mask. A LOCOS film formed by the first LOCOS process is removed to form narrower concavities under the side walls. Then, another silicon nitride film is deposited, and is removed leaving portions thereof forming the concavities. Then, a second LOCOS process is carried out to form a LOCOS film as an element isolating region. The second LOCOS process uses the oxidation mask having the narrow cavities, so that stress at the boundary of the active region and the element isolation region is reduced, and the growth of bird's beaks can be suppressed.

摘要翻译： 在形成SOI衬底的硅半导体层中的元件隔离区域时，在形成于SOI层上的氧化物膜上沉积预定厚度的氮化硅膜。 以活性区域的设计尺寸对氮化硅膜进行构图，并且在图案化的氮化硅膜的侧表面上形成氮化硅膜的侧壁。 使用氮化物膜作为氧化掩模进行第一LOCOS工艺。 去除由第一LOCOS工艺形成的LOCOS膜，以在侧壁下形成更窄的凹面。 然后，沉积另一个氮化硅膜，并除去形成凹部的部分。 然后，进行第二LOCOS工艺以形成LOCOS膜作为元件隔离区。 第二LOCOS工艺使用具有窄腔的氧化掩模，使得有源区域和元件隔离区域的边界处的应力减小，并且可以抑制鸟喙的生长。

公开(公告)号：US07786534B2

公开(公告)日：2010-08-31

申请号：US12399062

申请日：2009-03-06

申请人： Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L27/01

CPC分类号： H01L21/84 ,  H01L21/743 ,  H01L23/585 ,  H01L27/1203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

摘要翻译： 沿着半导体芯片的周边部分与最上面的导线一起形成多个导电层和连接具有SOI结构的支撑衬底和最上面的线的多个布线层，从而围绕晶体管形成区域 形成。

公开(公告)号：US07535062B2

公开(公告)日：2009-05-19

申请号：US11619874

申请日：2007-01-04

申请人： Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L27/01

CPC分类号： H01L21/84 ,  H01L21/743 ,  H01L23/585 ,  H01L27/1203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

摘要翻译： 沿着半导体芯片的周边部分与最上面的导线一起形成多个导电层和连接具有SOI结构的支撑衬底和最上面的线的多个布线层，从而围绕晶体管形成区域 形成。

公开(公告)号：US20090051009A1

公开(公告)日：2009-02-26

申请号：US12254026

申请日：2008-10-20

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L29/8605

CPC分类号： H01L29/7833 ,  H01L21/761 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665

摘要： Formed on an insulator are an N− type semiconductor layer having a partial isolator formed on its surface and a P− type semiconductor layer having a partial isolator formed on its surface. Source/drain being P+ type semiconductor layers are provided on the semiconductor layer to form a PMOS transistor. Source/drain being N+ type semiconductor layers are provided on the semiconductor layer to form an NMOS transistor. A pn junction formed by the semiconductor layers is provided in a CMOS transistor made up of the transistors. The pn junction is positioned separately from the partial isolators where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction.

摘要翻译： 在绝缘体上形成有在其表面上形成有部分隔离体的N-型半导体层，以及在其表面上形成有部分隔离体的P-型半导体层。 源极/漏极是P +型半导体层，设置在半导体层上以形成PMOS晶体管。 源极/漏极是N +型半导体层，设置在半导体层上以形成NMOS晶体管。 由半导体层形成的pn结设置在由晶体管构成的CMOS晶体管中。 pn结与部分隔离器分开定位，因此晶体缺陷非常小。 因此，在pn结处漏电流非常低。

公开(公告)号：US07453135B2

公开(公告)日：2008-11-18

申请号：US11617936

申请日：2006-12-29

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L29/93

CPC分类号： H01L27/0617 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/10 ,  H01L28/20 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.

摘要翻译： 多个沟槽隔离膜在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层的表面中设置有SOI层的部分。 电阻元件分别形成在沟槽隔离膜上。 每个沟槽隔离膜包括穿过SOI层并到达掩埋氧化膜以包括全沟槽隔离结构的中心部分，以及相对的侧部，其每个仅穿过SOI层的一部分并且位于 在SOI层上以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜包括混合沟槽隔离结构。

公开(公告)号：US07449749B2

公开(公告)日：2008-11-11

申请号：US11448827

申请日：2006-06-08

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/7833 ,  H01L21/761 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665

摘要： Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).

摘要翻译： 在绝缘体（9）上形成的是具有形成在其表面上的部分隔离体的N + O - 型半导体层（10）和具有形成在其上的P型 - 半导体层（20） 形成在其表面上的部分隔离器。 在半导体层（10）上设置有源极/漏极（11,12）作为P +型半导体层，形成PMOS晶体管（1）。 在半导体层（20）上设置有N +型半导体层的源极/漏极（21,22），以形成NMOS晶体管（2）。 由半导体层（10,20）形成的pn结（J 5）设置在由晶体管（1,2）构成的CMOS晶体管（100）中。 pn结（J 5）与部分隔离物（41,42）分开定位，因此晶体缺陷非常小。 因此，在pn结处漏电流非常低（J 5）。