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    Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same
    81.
    发明授权
    Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same 有权
    具有减少边界缺陷的混合取向半导体结构及其形成方法

    公开(公告)号：US08236636B2

    公开(公告)日：2012-08-07

    申请号：US12972771

    申请日：2010-12-20

    申请人： Haizhou Yin ,  John A. Ott ,  Katherine L. Saenger ,  Chun-Yung Sung

    发明人： Haizhou Yin ,  John A. Ott ,  Katherine L. Saenger ,  Chun-Yung Sung

    IPC分类号： H01L21/336

    CPC分类号： H01L21/02694 ,  H01L21/02532 ,  H01L21/76264 ,  Y10S438/973

    摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane direction of the (011) DSB layer is aligned with an in-plane direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane directions of the (001) base substrate, followed by recrystallization using the base substrate as a template. This optimal arrangement of DSB layer, base substrate, and amorphized region orientation provides a near-vertical, essentially defect-free boundary between original-orientation and changed-orientation silicon regions, thus enabling complete boundary region removal with smaller footprint shallow trench isolation than possible with ATR methods not so optimized.

    摘要翻译： 本发明提供用于形成混合取向基板和半导体器件结构的改进的非晶化/模板重结晶（ATR）方法。 具有（011）表面晶体取向的直接硅键合（DSB）硅层被结合到具有（001）表面晶体取向的基底硅基板上，以形成其中面内<110>方向的DSB晶片 （011）DSB层与（001）基底的面内<110>方向对准。 DSB层的选定区域被非晶化到底部基板以形成与（001）基底基板的相互正交的平面内100°方向对准的非晶形区域，然后使用基底基板作为模板进行重结晶。 DSB层，基底和非晶区域取向的这种最佳布置提供了原始取向和改变取向硅区域之间近似垂直的，基本上无缺陷的边界，因此可以实现完整的边界区域移除，并且可以实现更小的占地面积的浅沟槽隔离 ATR方法没有如此优化。

    Asymmetric source and drain field effect structure
    82.
    发明授权
    Asymmetric source and drain field effect structure 有权
    不对称源极和漏极场效应结构

    公开(公告)号：US07977712B2

    公开(公告)日：2011-07-12

    申请号：US12059059

    申请日：2008-03-31

    申请人： Huilong Zhu ,  Hong Lin ,  Katherine L. Saenger ,  Kai Xiu ,  Haizhou Yin

    发明人： Huilong Zhu ,  Hong Lin ,  Katherine L. Saenger ,  Kai Xiu ,  Haizhou Yin

    IPC分类号： H01L29/04

    CPC分类号： H01L21/823807 ,  H01L21/28132 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

    摘要： A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions.

    摘要翻译： 诸如CMOS半导体结构的半导体结构包括具有不对称的多个源区和漏区的场效应器件。 通过使用包括与倾斜斜面区域相邻并相邻的水平平台区域的半导体衬底制造半导体结构来诱导这种源区和漏区不对称。 在CMOS半导体结构的上下文中，这种半导体衬底允许在不同的晶体取向半导体区域上制造pFET和nFET，而pFET和nFET（即，通常为pFET）中的一个具有不对称的源极和漏极区域 。

    AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES
    83.
    发明申请
    AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES 有权
    用于混合定向衬底的拟合/调制再结晶方法

    公开(公告)号：US20100203708A1

    公开(公告)日：2010-08-12

    申请号：US12767261

    申请日：2010-04-26

    申请人： Keith Edward Fogel ,  Katherine L. Saenger ,  Chun-Yung Sung ,  Haizhou Yin

    发明人： Keith Edward Fogel ,  Katherine L. Saenger ,  Chun-Yung Sung ,  Haizhou Yin

    IPC分类号： H01L21/26 ,  H01L21/322

    CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

    摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.

    摘要翻译： 本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。 用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。 第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。 本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽界定的非晶化Si区域的边缘产生“角缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。 特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

    FIELD EFFECT TRANSISTOR USING CARBON BASED STRESS LINER
    87.
    发明申请
    FIELD EFFECT TRANSISTOR USING CARBON BASED STRESS LINER 有权
    使用碳基应力衬里的场效应晶体管

    公开(公告)号：US20080303068A1

    公开(公告)日：2008-12-11

    申请号：US11760030

    申请日：2007-06-08

    申请人： Alfred Grill ,  Son Nguyen ,  Katherine L. Saenger

    发明人： Alfred Grill ,  Son Nguyen ,  Katherine L. Saenger

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823807 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： A stress liner for use within a semiconductor structure that includes a field effect device has a dielectric constant less than about 7 and a compressive stress greater than about 5 GPa. The stress liner may be formed of a carbon based material, preferably a tetrahedral amorphous carbon (ta-C) material including at least about 60 atomic percent carbon and no greater than C about 40 atomic percent hydrogen. The carbon based material may be either a dielectric material, or given appropriate additional dielectric isolation structures, a semiconductor material. In particular, a ta-C stress liner may be formed using a filtered cathodic vacuum arc (FCVA) physical vapor deposition (PVD) method.

    摘要翻译： 在包括场效应器件的半导体结构内使用的应力衬垫具有小于约7的介电常数和大于约5GPa的压缩应力。 应力衬垫可以由碳基材料形成，优选地包括至少约60原子％的碳和不大于约40原子％的氢的四面体无定形碳（ta-C）材料。 碳基材料可以是介电材料，也可以是适当的另外的绝缘隔离结构，半导体材料。 特别地，可以使用过滤的阴极真空电弧（FCVA）物理气相沉积（PVD）方法形成ta-C应力衬垫。

    Mixed orientation and mixed material semiconductor-on-insulator wafer
    88.
    发明授权
    Mixed orientation and mixed material semiconductor-on-insulator wafer 有权
    混合取向和混合材料绝缘体上半导体晶片

    公开(公告)号：US07449767B2

    公开(公告)日：2008-11-11

    申请号：US11522905

    申请日：2006-09-19

    申请人： Guy M. Cohen ,  Alexander Reznicek ,  Katherine L. Saenger ,  Min Yang

    发明人： Guy M. Cohen ,  Alexander Reznicek ,  Katherine L. Saenger ,  Min Yang

    IPC分类号： H01L29/04

    CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

    摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.

    摘要翻译： 本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。 根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。 根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。 还公开了用于制造本发明的不同实施例的方法和过程。

    UNIAXIAL STRAIN RELAXATION OF BIAXIAL-STRAINED THIN FILMS USING ION IMPLANTATION
    89.
    发明申请
    UNIAXIAL STRAIN RELAXATION OF BIAXIAL-STRAINED THIN FILMS USING ION IMPLANTATION 失效
    使用离子植入的双应变薄膜的单轴应变松弛

    公开(公告)号：US20080171426A1

    公开(公告)日：2008-07-17

    申请号：US11622524

    申请日：2007-01-12

    申请人： Zhibin Ren ,  Katherine L. Saenger ,  Haizhou Yin

    发明人： Zhibin Ren ,  Katherine L. Saenger ,  Haizhou Yin

    IPC分类号： H01L21/425

    CPC分类号： H01L21/26506 ,  H01L21/823807 ,  H01L29/78 ,  H01L29/7848 ,  Y10S438/938

    摘要： A method for achieving uniaxial strain on originally biaxial-strained thin films after uniaxial strain relaxation induced by ion implantation is provided. The biaxial-strained thin film receives ion implantation after being covered by a patterned implant block structure. The strain in the uncovered region is relaxed by ion implantation, which induces the lateral strain relaxation in the covered region. When the implant block structure is narrow (dimension is comparable to the film thickness), the original biaxial strain will relax uniaxially in the lateral direction.

    摘要翻译： 提供了一种通过离子注入诱发的单轴应变松弛之后在原始双轴应变薄膜上实现单轴应变的方法。 双轴应变薄膜在被图案化的植入物块结构覆盖之后接收离子注入。 未覆盖区域的应变通过离子注入而松弛，这引起覆盖区域的横向应变弛豫。 当植入物块结构窄（尺寸与膜厚度相当）时，原始双轴应变将在横向方向上单轴弛豫。

    Diaphragm activated micro-electromechanical switch
    90.
    发明授权
    Diaphragm activated micro-electromechanical switch 有权
    隔膜激活微机电开关

    公开(公告)号：US07256670B2

    公开(公告)日：2007-08-14

    申请号：US10523310

    申请日：2002-08-26

    申请人： Christopher V. Jahnes ,  Jennifer L. Lund ,  Katherine L. Saenger ,  Richard P. Volant

    发明人： Christopher V. Jahnes ,  Jennifer L. Lund ,  Katherine L. Saenger ,  Richard P. Volant

    IPC分类号： H01H51/22

    CPC分类号： H01H59/0009

    摘要： A micro-electromechanical (MEM) RF switch provided with a deflectable membrane (60) activates a switch contact or plunger (40). The membrane incorporates interdigitated metal electrodes (70) which cause a stress gradient in the membrane when activated by way of a DC electric field. The stress gradient results in a predictable bending or displacement of the membrane (60), and is used to mechanically displace the switch contact (30). An RF gap area (25) located within the cavity (250) is totally segregated from the gaps (71) between the interdigitated metal electrodes (70). The membrane is electrostatically displaced in two opposing directions, thereby aiding to activate and deactivate the switch. The micro-electromechanical switch includes: a cavity (250); at least one conductive path (20) integral to a first surface bordering the cavity; a flexible membrane (60) parallel to the first surface bordering the cavity (250), the flexible membrane (60) having a plurality of actuating electrodes (70); and a plunger (40) attached to the flexible membrane (60) in a direction away from the actuating electrodes (70), the plunger (40) having a conductive surface that makes electric contact with the conductive paths, opening and closing the switch.

    摘要翻译： 设置有可偏转膜（60）的微机电（MEM）RF开关激活开关触点或柱塞（40）。 膜包含交叉指向的金属电极（70），其通过DC电场激活时引起膜中的应力梯度。 应力梯度导致膜（60）的可预测的弯曲或位移，并且用于机械地移动开关触点（30）。 位于空腔（250）内的RF间隙区域（25）与交叉指向的金属电极（70）之间的间隙（71）完全分离。 膜在两个相反的方向上静电位移，从而有助于启动和停用开关。 微机电开关包括：空腔（250）; 至少一个导电通路（20），与所述空腔相邻的第一表面成一体; 柔性膜（60），其平行于与所述腔（250）接壤的所述第一表面，所述柔性膜（60）具有多个致动电极（70）; 以及沿远离所述致动电极（70）的方向附接到所述柔性膜（60）的柱塞（40），所述柱塞（40）具有导电表面，所述导电表面与所述导电路径电接触，所述开关闭合。