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382 条记录 (耗时 0.025 秒)

    Hetero-Bimos injection process for non-volatile flash memory
    86.
    发明申请
    Hetero-Bimos injection process for non-volatile flash memory 有权
    异质闪存注入过程

    公开(公告)号：US20080237735A1

    公开(公告)日：2008-10-02

    申请号：US11731162

    申请日：2007-03-30

    申请人： Jack T. Kavalieros ,  Suman Datta ,  Robert S. Chau ,  David L. Kencke

    发明人： Jack T. Kavalieros ,  Suman Datta ,  Robert S. Chau ,  David L. Kencke

    IPC分类号： H01L27/06 ,  H01L21/8249

    CPC分类号： H01L21/8249 ,  H01L21/28273 ,  H01L27/0705 ,  H01L29/0821 ,  H01L29/66825 ,  H01L29/73 ,  H01L29/7606 ,  H01L29/7881

    摘要： A hetero-BiMOS injection system comprises a MOSFET transistor formed on a substrate and a hetero-bipolar transistor formed within the substrate. The bipolar transistor can be used to inject charge carriers into a floating gate of the MOSFET transistor. This is done by operating the MOSFET transistor to form an inversion layer in its channel region and operating the bipolar transistor to drive minority charge carriers from the substrate into a floating gate of the MOSFET transistor. The substrate provides a silicon emitter and a silicon germanium containing base for the bipolar transistor. The inversion layer provides a silicon collector for the bipolar transistor.

    摘要翻译： 异质BiMOS注入系统包括形成在衬底上的MOSFET晶体管和形成在衬底内的异质双极晶体管。 双极晶体管可用于将电荷载流子注入MOSFET晶体管的浮置栅极。 这通过操作MOSFET晶体管在其沟道区域中形成反型层并且操作双极晶体管来驱动少数电荷载体从衬底驱动到MOSFET晶体管的浮置栅极。 衬底为双极晶体管提供硅发射极和含硅锗基底。 反型层为双极晶体管提供硅集电极。

    On-chip memory cell and method of manufacturing same
    87.
    发明申请
    On-chip memory cell and method of manufacturing same 审中-公开
    片上存储单元及其制造方法

    公开(公告)号：US20080237678A1

    公开(公告)日：2008-10-02

    申请号：US11729192

    申请日：2007-03-27

    申请人： Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Dinesh Somasekhar ,  Ali Keshavarzi

    发明人： Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Dinesh Somasekhar ,  Ali Keshavarzi

    IPC分类号： H01L27/108 ,  H01L21/336

    CPC分类号： H01L27/10873 ,  H01L27/10826 ,  H01L29/785

    摘要： An on-chip memory cell comprises a tri-gate access transistor (145) and a tri-gate capacitor (155). The on-chip memory cell may be an embedded DRAM on a three-dimensional tri-gate transistor and capacitor structures which is fully compatible with existing tri-gate logic transistor fabrication process. Embodiments of the invention use the high fin aspect ratio and inherently superior surface area of the tri-gate transistors to replace the “trench” capacitor in a commodity DRAM with an inversion mode tri-gate capacitor. The tall sidewalls of the tri-gate transistor provide large enough surface area to provide storage capacitance in a small cell area.

    摘要翻译： 片上存储单元包括三栅极存取晶体管（145）和三栅极电容器（155）。 片上存储器单元可以是三维三栅晶体管上的嵌入式DRAM和与现有三栅逻辑晶体管制造工艺完全兼容的电容器结构。 本发明的实施例使用三栅极晶体管的高翅片长宽比和固有优越的表面积来替代具有反向模式三栅极电容器的商品DRAM中的“沟槽”电容器。 三栅极晶体管的高侧壁提供足够大的表面积，以在小单元区域中提供存储电容。

    PINNING LAYER FOR LOW RESISTIVITY N-TYPE SOURCE DRAIN OHMIC CONTACTS
    89.
    发明申请
    PINNING LAYER FOR LOW RESISTIVITY N-TYPE SOURCE DRAIN OHMIC CONTACTS 有权
    密封层用于低电阻N型源漏管OHMIC接触

    公开(公告)号：US20080017891A1

    公开(公告)日：2008-01-24

    申请号：US11480667

    申请日：2006-06-30

    申请人： Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau ,  Mark L. Doczy

    发明人： Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau ,  Mark L. Doczy

    IPC分类号： H01L29/76 ,  H01L29/745

    CPC分类号： H01L29/0847 ,  H01L21/28525 ,  H01L29/7833

    摘要： A system or apparatus including an N-type transistor structure including a gate electrode formed on a substrate and source and drain regions formed in the substrate; a contact to the source region; and a pinning layer disposed between the source region and the first contact and defining an interface between the pinning layer and the source region, wherein the pinning layer has donor-type surface states in a conduction band. A method including forming a transistor structure including a gate electrode on a substrate and source and drain regions formed in the substrate; depositing a pinning layer having donor-type surface states on the source and drain regions such that an interface is defined between the pinning layer and the respective one of the source and drain regions; and forming a first contact to the source region and a second contact to the drain region.

    摘要翻译： 一种包括N型晶体管结构的系统或装置，包括形成在衬底上的栅电极和形成在衬底中的源区和漏区; 与源区的联系; 以及钉扎层，其设置在所述源区域和所述第一触点之间并且限定所述钉扎层和所述源区域之间的界面，其中所述钉扎层在导带中具有施主型表面状态。 一种包括在衬底上形成包括栅电极的晶体管结构和形成在衬底中的源极和漏极区的方法; 在源极和漏极区域上沉积具有施主型表面状态的钉扎层，使得在钉扎层与源极和漏极区域中的相应一个之间界定界面; 以及向所述源极区域形成第一接触和向所述漏极区域形成第二接触。