公开(公告)号：US20090073791A1

公开(公告)日：2009-03-19

申请号：US12274570

申请日：2008-11-20

申请人： Shigeki Tomishima

发明人： Shigeki Tomishima

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C7/062 ,  G11C7/1048 ,  G11C2207/063

摘要： Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output (LIO) line and a global input/output (GIO) line each having first and second signal lines. A source follower circuit, coupled between the LIO line and the GIO line, includes first and second n-channel MOS (NMOS) transistors having a drain coupled to the first and the second signal lines of the GIO and a gate coupled to the first and the second signal lines of the LIO. A third NMOS transistor has a source coupled to the source of the first and the second NMOS transistors, a gate coupled to a reference voltage supply and a drain coupled to a drain of a fourth NMOS transistor. The fourth NMOS has a gate to which a selection signal is applied and a source coupled to a ground.

摘要翻译： 提供了方法，电路，器件和系统，包括低电压数据通路和电流检测放大器。 一个数据路径包括本地输入/输出（LIO）线和全局输入/输出（GIO）线，每条线具有第一和第二信号线。 耦合在LIO线路和GIO线路之间的源极跟随器电路包括第一和第二n沟道MOS（NMOS）晶体管，其具有耦合到GIO的第一和第二信号线的漏极和耦合到第一和 LIO的第二条信号线。 第三NMOS晶体管具有耦合到第一和第二NMOS晶体管的源极的源极，耦合到参考电压源的栅极和耦合到第四NMOS晶体管的漏极的漏极。 第四NMOS具有施加选择信号的栅极和耦合到地的源极。

公开(公告)号：US07177213B2

公开(公告)日：2007-02-13

申请号：US10958936

申请日：2004-10-05

申请人： Shigeki Tomishima

发明人： Shigeki Tomishima

IPC分类号： G11C7/00

CPC分类号： G11C11/4094 ,  G11C7/12

摘要： Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selecting the size of a capacitor in the precharge circuit.

摘要翻译： 提供电路和方法用于对存储器数字线对进行预充电。 数字线的最终预充电电压与预充电之前的数字线电压的平均值不同。 可以通过适当选择预充电电路中的电容器的尺寸来设定最终预充电电压。

公开(公告)号：US20060209604A1

公开(公告)日：2006-09-21

申请号：US11084345

申请日：2005-03-17

申请人： Shigeki Tomishima

发明人： Shigeki Tomishima

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C2207/005

摘要： A system and method to reduce standby leakage current in the event of row-to-column shorts in a memory chip or in an electronic device having memory or data storage elements is disclosed. In case of memory rows or wordlines precharged to a negative wordline voltage (VNWL), the standby leakage current through Psense-amplifiers in the memory is substantially eliminated when the gates of isolation (ISO) transistors associated with the shorted wordline and digitline(s) are held at the VNWL level by an isolation signal driven to the VNWL level during the memory row standby state. The reduction in the standby leakage current further reduces the overall Icc current consumption from the memory circuit's supply or operating voltage Vcc, thereby reducing circuit's standby power consumption. Because the ISO gates are already fabricated with thick oxides, the present negative voltage driving methodology does not require modifying the sense amplifier layout or the configuration of existing isolation transistors in a memory chip. A different standby voltage level (Vcc/2 level) at the sense amplifier activation (ACT) signal may also be implemented. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 公开了一种在存储器芯片或具有存储器或数据存储元件的电子设备中的行到列短路的情况下减少备用漏电流的系统和方法。 在预充电到负字线电压（VNWL）的存储器行或字线的情况下，当与短路字线和数字线相关联的隔离（ISO）晶体管的栅极时，基本上消除了通过存储器中的信号放大器的待机漏电流， 在VNWL级别通过在内存行待机状态下驱动到VNWL级别的隔离信号保持在VNWL级别。 待机漏电流的减少进一步降低了存储电路的供电或工作电压Vcc的总体Icc电流消耗，从而降低了电路的待机功耗。 由于ISO栅极已经用厚的氧化物制造，所以目前的负电压驱动方法不需要修改存储器芯片中的读出放大器布局或现有隔离晶体管的配置。 还可以实现在感测放大器激活（ACT）信号处的不同待机电压电平（Vcc / 2电平）。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US06885235B2

公开(公告)日：2005-04-26

申请号：US10095080

申请日：2002-03-12

申请人： Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Hiroaki Tanizaki ,  Tsukasa Ooishi

发明人： Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Hiroaki Tanizaki ,  Tsukasa Ooishi

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C29/06 ,  G05F3/04

CPC分类号： G11C5/147

摘要： An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.

摘要翻译： 内部电源电位产生电路包括连接到内部电源节点的过充电防止电路。 过充电防止电路包括输出由内部电源电位确定的待确定信号的电路，放大要确定的信号之间的电位差和作为输出到节点的参考电位的差分放大电路作为信号 表示应该绘制电流，并且响应于指示应当绘制电流的信号，从内部电源节点抽出电流的电流绘制电路。 因此，感兴趣的半导体集成电路器件可以提供稳定的内部电源电位。

公开(公告)号：US06861708B2

公开(公告)日：2005-03-01

申请号：US10383578

申请日：2003-03-10

申请人： Shigeki Tomishima

发明人： Shigeki Tomishima

IPC分类号： H01L21/762 ,  G11C11/404 ,  G11C11/407 ,  H01L21/02 ,  H01L21/265 ,  H01L21/76 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/02 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/10882 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/10814 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/78612

摘要： This semiconductor device is provided with a wiring called a body line (BDL), a body section of a memory cell transistor is connected to this body line (BDL), and a potential of the body section is controlled by a body section controller connected to the body line. As a result, it is possible to propose a novel structure capable of keeping the potential of the body section low and to provide a semiconductor device and a manufacturing method therefor, capable of improving operation performance by contriving circuit operation.

摘要翻译： 该半导体装置设置有称为体线（BDL）的布线，存储单元晶体管的主体部分连接到该体线（BDL），并且主体部分的电位由连接到 身体线。 结果，可以提出能够将体部的电位保持为低的新型结构，并提供能够通过设计电路操作来提高操作性能的半导体器件及其制造方法。

公开(公告)号：US06646946B2

公开(公告)日：2003-11-11

申请号：US09976335

申请日：2001-10-15

申请人： Shigeki Tomishima ,  Tsukasa Ooishi ,  Hiroshi Kato

发明人： Shigeki Tomishima ,  Tsukasa Ooishi ,  Hiroshi Kato

IPC分类号： G11C800

CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C8/12

摘要： A memory array is divided into a plurality of memory sub blocks in row and column directions. A column selection line is provided in the column direction in a region between blocks. A block decoding circuit generating a local column selection signal is arranged corresponding to each of the memory sub blocks. A main I/O line pair group is provided for each of the memory sub blocks and each column of the memory sub block is connected to the corresponding main I/O line pair in accordance with the local column selection line. Thus, data with a desired bit width can be produced without any increase in area occupied by the array nor decrease in the speed of column access.

公开(公告)号：US06618319B2

公开(公告)日：2003-09-09

申请号：US10209894

申请日：2002-08-02

申请人： Tsukasa Ooishi ,  Masatoshi Ishikawa ,  Shigeki Tomishima

发明人： Tsukasa Ooishi ,  Masatoshi Ishikawa ,  Shigeki Tomishima

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C11/4076

摘要： For a write operation, a synchronous semiconductor memory device in a single-data-rate SDRAM operation mode selects a memory cell column in accordance with a column select signal produced from a write clock produced in synchronization with an external clock signal without shifting the write clock. In a double-data-rate SDRAM operation mode, the synchronous semiconductor memory device selects the memory cell column in accordance with the column select signal produced from the write clock produced in synchronization with the external clock signal and shifted by selected clocks.

公开(公告)号：US06545926B2

公开(公告)日：2003-04-08

申请号：US09197566

申请日：1998-11-23

申请人： Tsukasa Ooishi ,  Hiroki Shimano ,  Hideto Hidaka ,  Shigeki Tomishima

发明人： Tsukasa Ooishi ,  Hiroki Shimano ,  Hideto Hidaka ,  Shigeki Tomishima

IPC分类号： G11C700

CPC分类号： G11C29/70

摘要： An input protective circuit in a semiconductor integrated circuit device includes a bipolar transistor arranged for an interconnection layer. An N-type active region in the bipolar transistor is connected to an electrode of a program element. The electrode is connected to the interconnection layer. The interconnection layer supplies a high voltage for breaking a dielectric of a program element. A voltage on a P-type well is externally adjusted via a resistance element. Thereby, erroneous program due to serge entering at the interconnection layer can be avoided.

摘要翻译： 半导体集成电路器件中的输入保护电路包括布置成互连层的双极晶体管。 双极晶体管中的N型有源区连接到程序元件的电极。 电极连接到互连层。 互连层提供用于断开程序元件的电介质的高电压。 通过电阻元件外部调整P型阱上的电压。 因此，可以避免由于在互连层处进入的错误程序。

公开(公告)号：US06470467B2

公开(公告)日：2002-10-22

申请号：US09349260

申请日：1999-07-08

申请人： Shigeki Tomishima ,  Tsukasa Ooishi

发明人： Shigeki Tomishima ,  Tsukasa Ooishi

IPC分类号： G06F1100

CPC分类号： G11C29/12 ,  G11C29/14 ,  G11C29/36 ,  G11C29/48

摘要： A driver circuit applies a write data whose level is inverted for every write cycle to a selected memory cell in accordance with a write data held by a latch circuit when a writing operation in a test operation mode is designated in the test operation mode. A read driver circuit applies a comparison result of sequentially read data to a latch circuit in accordance with a read clock signal in the test operation mode. Data input and output buffers operate in synchronization with an external clock signal.

摘要翻译： 当在测试操作模式中指定测试操作模式中的写入操作时，驱动器电路根据由锁存电路保持的写入数据，将每个写入周期的电平反转的写数据应用于所选存储单元。 读取驱动器电路根据测试操作模式中的读取时钟信号将顺序读取数据的比较结果应用于锁存电路。 数据输入和输出缓冲器与外部时钟信号同步工作。

公开(公告)号：US06466509B1

公开(公告)日：2002-10-15

申请号：US10050131

申请日：2002-01-18

申请人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C11/4087 ,  G11C2207/104

摘要： First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.

摘要翻译： 第一和第二存储体设置有M个存储块，每个存储块具有第一和第二存储区域，M表示偶数个不少于两个，以及（M + 1）个读出放大器频带，其布置在每个存储块的相对侧上，并具有 第一选择线和第二选择线分别用于选择第一和第二存储区，第一选择线连接到第一存储体的奇数读出放大器带和第二存储体的偶数读出放大器带 第二选择线连接到第一存储体的偶数读出放大器带和第二存储体的奇数读出放大器带。