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公开(公告)号：US06314042B1
公开(公告)日：2001-11-06
申请号：US09181675
申请日：1998-10-29
申请人： Shigeki Tomishima , Tsukasa Ooishi , Hiroshi Kato
发明人： Shigeki Tomishima , Tsukasa Ooishi , Hiroshi Kato
IPC分类号： G11C800
CPC分类号： G11C11/4097 , G11C7/1006 , G11C8/12
摘要： A memory array is divided into a plurality of memory sub blocks in row and column directions. A column selection line is provided in the column direction in a region between blocks. A block decoding circuit generating a local column selection signal is arranged corresponding to each of the memory sub blocks. A main I/O line pair group is provided for each of the memory sub blocks and each column of the memory sub block is connected to the corresponding main I/O line pair in accordance with the local column selection line. Thus, data with a desired bit width can be produced without any increase in area occupied by the array nor decrease in the speed of column access.
摘要翻译： 存储器阵列被划分成行和列方向上的多个存储器子块。 在块方向之间的区域中，在列方向上设置列选择线。 产生本地列选择信号的块解码电路对应于每个存储子块排列。 为每个存储器子块提供主I / O线对组，并且根据本地列选择线将存储器子块的每一列连接到对应的主I / O线对。 因此，可以产生具有期望比特宽度的数据，而不会增加阵列占用的面积，也不降低列访问的速度。
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2.发明授权Semiconductor memory device capable of high speed operation and including redundant cells 有权半导体存储器件能够高速运行并且包括冗余单元
公开(公告)号：US6058053A
公开(公告)日：2000-05-02
申请号：US195212
申请日：1998-11-18
CPC分类号： G11C29/84 , G11C29/844
摘要： In the semiconductor memory device, independent from redundancy determination by a redundancy determining circuit, a word line activating signal (subdecode signal) for setting a word line in a normal block corresponding to a decoded address signal, is activated. A WL driver includes a driver portion for selecting a word line in the normal block, and a driver portion for selecting a spare word line in a redundant block. When redundancy is not to be used as a result of redundancy determination by the redundancy determining circuit, activated subdecode signal is inactivated. If redundancy is to be used as a result of redundancy determination, a corresponding word line is set to the selected state, using the activated subdecode signal. Thus a semiconductor memory device in which substitution can be done at high speed with high efficiency is provided.
摘要翻译： 在半导体存储器件中，独立于由冗余确定电路进行的冗余确定，激活用于设置与解码的地址信号对应的正常块中的字线的字线激活信号（子代码信号）。 WL驱动器包括用于选择正常块中的字线的驱动器部分和用于在冗余块中选择备用字线的驱动器部分。 作为由冗余确定电路的冗余确定的结果不使用冗余时，激活的子代码信号被去激活。 如果作为冗余确定的结果使用冗余，则使用激活的子代码信号将对应的字线设置为所选择的状态。 因此，提供了可以以高效率高效率地进行替换的半导体存储器件。
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3.发明授权Semiconductor integrated circuit device with internal power supply potential generation circuit 失效具有内部电源电位生成电路的半导体集成电路器件公开(公告)号：US06885235B2
公开(公告)日：2005-04-26
申请号：US10095080
申请日：2002-03-12
申请人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
发明人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C29/06 , G05F3/04
CPC分类号： G11C5/147
摘要： An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.
摘要翻译： 内部电源电位产生电路包括连接到内部电源节点的过充电防止电路。 过充电防止电路包括输出由内部电源电位确定的待确定信号的电路，放大要确定的信号之间的电位差和作为输出到节点的参考电位的差分放大电路作为信号 表示应该绘制电流，并且响应于指示应当绘制电流的信号，从内部电源节点抽出电流的电流绘制电路。 因此，感兴趣的半导体集成电路器件可以提供稳定的内部电源电位。
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公开(公告)号：US06646946B2
公开(公告)日：2003-11-11
申请号：US09976335
申请日：2001-10-15
申请人： Shigeki Tomishima , Tsukasa Ooishi , Hiroshi Kato
发明人： Shigeki Tomishima , Tsukasa Ooishi , Hiroshi Kato
IPC分类号： G11C800
CPC分类号： G11C11/4097 , G11C7/1006 , G11C8/12
摘要： A memory array is divided into a plurality of memory sub blocks in row and column directions. A column selection line is provided in the column direction in a region between blocks. A block decoding circuit generating a local column selection signal is arranged corresponding to each of the memory sub blocks. A main I/O line pair group is provided for each of the memory sub blocks and each column of the memory sub block is connected to the corresponding main I/O line pair in accordance with the local column selection line. Thus, data with a desired bit width can be produced without any increase in area occupied by the array nor decrease in the speed of column access.
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5.发明授权Semiconductor memory device having a column select line transmitting a column select signal 失效具有发送列选择信号的列选择线的半导体存储器件公开(公告)号：US06466509B1
公开(公告)日：2002-10-15
申请号：US10050131
申请日：2002-01-18
申请人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C11/4087 , G11C2207/104
摘要： First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.
摘要翻译： 第一和第二存储体设置有M个存储块，每个存储块具有第一和第二存储区域，M表示偶数个不少于两个，以及（M + 1）个读出放大器频带，其布置在每个存储块的相对侧上，并具有 第一选择线和第二选择线分别用于选择第一和第二存储区，第一选择线连接到第一存储体的奇数读出放大器带和第二存储体的偶数读出放大器带 第二选择线连接到第一存储体的偶数读出放大器带和第二存储体的奇数读出放大器带。
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6.发明授权Semiconductor memory device capable of reducing leakage current flowing into substrate 失效能够减少流入基板的漏电流的半导体存储器件公开(公告)号：US06411560B1
公开(公告)日：2002-06-25
申请号：US09987277
申请日：2001-11-14
申请人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
IPC分类号： G11C514
CPC分类号： G11C7/1096 , G11C5/146 , G11C5/147 , G11C7/1078 , G11C7/22 , G11C8/10 , G11C11/4074
摘要： A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [1], a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.
摘要翻译： 第一电源电压被提供给读出放大器的电源节点。 位线驱动器将由第二电源电压组成的列选择信号输出到GIO线路电路的N沟道MOS晶体管的栅极端子。 当输入/输出数据为[1]时，低于第一电源电压的第三电源电压被提供给全局数据线。 在这种情况下，利用所使用的N沟道MOS晶体管的阈值电压，建立关系：第二电源电压<=第三电源电压+阈值电压。 结果，在由具有不同电压电平的多个电源电压驱动的半导体存储器件中，可以减小泄漏电流。
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7.发明授权Semiconductor device including a fuse circuit in which the electric current is cut off after blowing so as to prevent voltage fall 失效包括熔断电路的半导体装置，其中在吹风之后切断电流以防止电压下降公开(公告)号：US06400632B1
公开(公告)日：2002-06-04
申请号：US09820853
申请日：2001-03-30
IPC分类号： G11C700
摘要： The antifuse is brought into an electrically conducted state by setting the voltage Vpgm to a high voltage after activating the signal SA and setting the node N1 once to an L-level. By inversion of the latch, the voltage of the node N1 will be the power source voltage Vcc to bring the transistor into a non-conducted state, whereby the electric current flowing through the antifuse is cut off. A semiconductor device can be provided which includes an antifuse program circuit capable of cutting the electric current off after blowing, so as to prevent decrease in the blowing voltage.
摘要翻译： 通过在激活信号SA之后将电压Vpgm设置为高电压并将节点N1设置为L电平，将反熔丝导入导电状态。 通过锁存器的反相，节点N1的电压将是电源电压Vcc，以使晶体管进入非导通状态，从而切断流过反熔丝的电流。 可以提供一种半导体器件，其包括能够在吹制之后切断电流的反熔丝程序电路，以防止吹送电压的降低。
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公开(公告)号：US06859403B2
公开(公告)日：2005-02-22
申请号：US10815798
申请日：2004-04-02
申请人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
发明人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
IPC分类号： G11C11/407 , G11C5/14 , G11C7/06 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/401 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108
CPC分类号： G11C11/4085 , G11C5/14 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/4074 , G11C11/4091
摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.
摘要翻译： 第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。 第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。 第二晶体管在其栅极处接收内部产生的信号，其源极接地。 在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为 导通，以防止感测驱动线从虚拟GND电位Vss'浮起。
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公开(公告)号：US06480946B1
公开(公告)日：2002-11-12
申请号：US09283758
申请日：1999-04-02
IPC分类号： G06F1200
CPC分类号： G11C7/1066 , G11C5/063 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A plurality of memory devices are connected parallel to each other commonly to signal lines extending in one direction, and signals are transmitted in one direction along the signal lines. The sum of the time of signal propagation from a transmission unit to a selected memory device and the time of signal propagation from the selected memory devices to a reception unit is constant for every memory device. Therefore, offset in access times to the memory chips in the memory system can be eliminated.
摘要翻译： 多个存储器件共同并联连接以使在一个方向上延伸的信号线信号沿着信号线沿一个方向传输。 从传输单元到所选择的存储器件的信号传播的时间和从选择的存储器件到接收单元的信号传播的时间的总和对于每个存储器件是恒定的。 因此，可以消除对存储器系统中的存储器芯片的访问时间的偏移。
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10.发明授权公开(公告)号：US06438066B1
公开(公告)日：2002-08-20
申请号：US09641901
申请日：2000-08-18
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C11/4076
摘要： For a write operation, a synchronous semiconductor memory device in a single-data-rate SDRAM operation mode selects a memory cell column in accordance with a column select signal produced from a write clock produced in synchronization with an external clock signal without shifting the write clock. In a double-data-rate SDRAM operation mode, the synchronous semiconductor memory device selects the memory cell column in accordance with the column select signal produced from the write clock produced in synchronization with the external clock signal and shifted by selected clocks.
摘要翻译： 对于写入操作，单数据速率SDRAM操作模式的同步半导体存储器件根据从与外部时钟信号同步产生的写时钟产生的列选择信号选择存储单元列，而不移位写时钟 。 在双数据速率SDRAM操作模式中，同步半导体存储器件根据与外部时钟信号同步产生的写入时钟产生的列选择信号选择存储单元列，并移位选定的时钟。
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