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    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
    81.
    发明申请
    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200371937A1

    公开(公告)日：2020-11-26

    申请号：US16879264

    申请日：2020-05-20

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/0842 ,  G06F12/0888 ,  G06F12/0811

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM
    82.
    发明申请
    PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM 审中-公开

    公开(公告)号：US20200057720A1

    公开(公告)日：2020-02-20

    申请号：US16102862

    申请日：2018-08-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung ONG

    IPC: G06F12/0862 ,  G06F12/0811 ,  G06F9/38

    Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

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