公开(公告)号：US20220093770A1

公开(公告)日：2022-03-24

申请号：US17190267

申请日：2021-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  C23C18/16

Abstract: Embodiments utilize an electro-chemical process to deposit a metal gate electrode in a gate opening in a gate replacement process for a nanosheet FinFET device. Accelerators and suppressors may be used to achieve a bottom-up deposition for a fill material of the metal gate electrode.

公开(公告)号：US20210408043A1

公开(公告)日：2021-12-30

申请号：US17106516

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L21/28 ,  H01L29/78

Abstract: A device includes a first channel; a second channel above the first channel; and a gate structure surrounding the first and second channels, wherein the gate structure includes a ferroelectric (FE) layer surrounding the first and second channels and a gate metal layer surrounding the FE layer. The device further includes two first electrodes connected to two sides of the first channel; two second electrodes connected to two sides of the second channel; a dielectric layer between the first and the second electrodes; and an inner spacer layer between the two first electrodes and the gate structure.

公开(公告)号：US20210375629A1

公开(公告)日：2021-12-02

申请号：US17094241

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/3115 ,  H01L21/8234 ,  H01L29/51 ,  H01L27/088

Abstract: A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.

公开(公告)号：US20210280415A1

公开(公告)日：2021-09-09

申请号：US17321691

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yen Peng ,  Te-Yang Lai ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78

Abstract: A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.

公开(公告)号：US20210273070A1

公开(公告)日：2021-09-02

申请号：US16889217

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hung-Chin Chung ,  Chung-Chiang Wu ,  Hsuan-Yu Tung ,  Kuan-Chang Chiu ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

公开(公告)号：US20210265489A1

公开(公告)日：2021-08-26

申请号：US16906546

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/764

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, and forming a sacrificial film over the first semiconductor layer and the second semiconductor layer. The sacrificial film fills an area between the first semiconductor layer and the second semiconductor layer. The method further includes forming a space in the sacrificial film between the first semiconductor layer and the second semiconductor layer and removing the sacrificial film.

公开(公告)号：US20210242327A1

公开(公告)日：2021-08-05

申请号：US16940226

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

公开(公告)号：US20210202697A1

公开(公告)日：2021-07-01

申请号：US16806366

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/265

Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

公开(公告)号：US20210202511A1

公开(公告)日：2021-07-01

申请号：US16904717

申请日：2020-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi On Chui ,  Chenchen Jacob Wang

IPC: H01L27/11509 ,  H01L27/11507 ,  H01L49/02

Abstract: A semiconductor device includes: a substrate; a first dielectric layer over the substrate; a memory cell over the substrate in a first region of the semiconductor device, where the memory cell includes a first ferroelectric structure in the first dielectric layer, where the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer in between; and a tunable capacitor over the substrate in a second region of the semiconductor device, where the tunable capacitor includes a second ferroelectric structure, where the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer in between, where at least a portion of the second ferroelectric structure is in the first dielectric layer.

公开(公告)号：US10818658B2

公开(公告)日：2020-10-27

申请号：US16045266

申请日：2018-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Ying-Keung Leung ,  Chi On Chui

IPC: H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/32 ,  H01L21/3105

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.