公开(公告)号：US20230371261A1

公开(公告)日：2023-11-16

申请号：US18358365

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H01L29/792 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L29/51 ,  H01L23/532 ,  H01L21/28

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H01L23/528 ,  H01L21/76877 ,  H01L21/31111 ,  H01L29/518 ,  H10B43/27 ,  H01L21/76834 ,  H01L29/513 ,  H01L23/53257 ,  H01L29/40117

Abstract: A semiconductor device and method of forming thereof that includes a transistor of a peripheral circuit on a substrate. A first interconnect structure such as a first access line is formed over the transistor. A via extends above the first access line. A plurality of memory cell structures is formed over the interconnect structure and the via. A second interconnect structure, such as a second access line, is formed over the memory cell structure. The first access line is coupled to a first memory cell of the plurality of memory cell structures and second access line is coupled to a second memory cell of the plurality of memory cell structures.

公开(公告)号：US11791335B2

公开(公告)日：2023-10-17

申请号：US17327123

申请日：2021-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/48 ,  H01L29/06 ,  H01L27/06 ,  H01L29/66 ,  H01L27/11 ,  H01L49/02 ,  H01L21/8234 ,  H10B10/00 ,  H10B61/00 ,  H10N59/00 ,  H01L21/8258

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/5226 ,  H01L27/0688 ,  H01L28/40 ,  H01L29/0653 ,  H01L29/66545 ,  H10B10/12 ,  H10B61/00 ,  H10N59/00 ,  H01L21/8258 ,  H01L27/0605

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

公开(公告)号：US11716855B2

公开(公告)日：2023-08-01

申请号：US17133964

申请日：2020-12-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia Yu Ling ,  Chung-Te Lin ,  Katherine H. Chiang

IPC: H10B51/20 ,  H01L29/06 ,  G11C11/22 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  G11C11/2255 ,  G11C11/2257 ,  H01L29/0649 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a pair of dielectric layers; a word line between the dielectric layers, sidewalls of the dielectric layers being recessed from a sidewall of the word line; a tunneling strip on a top surface of the word line, the sidewall of the word line, a bottom surface of the word line, and the sidewalls of the dielectric layers; a semiconductor strip on the tunneling strip; a bit line contacting a sidewall of the semiconductor strip; and a source line contacting the sidewall of the semiconductor strip.

公开(公告)号：US20230076806A1

公开(公告)日：2023-03-09

申请号：US17981608

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L23/522 ,  H01L27/1159 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/11578

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US11527553B2

公开(公告)日：2022-12-13

申请号：US17140888

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/417 ,  H01L27/11585 ,  H01L27/11587

Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

公开(公告)号：US20220367517A1

公开(公告)日：2022-11-17

申请号：US17874844

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L23/522 ,  H01L27/1159 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/11578

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US11495619B2

公开(公告)日：2022-11-08

申请号：US17103532

申请日：2020-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Chun-Chen Chen ,  Po-Hsiang Huang ,  Lee-Chung Lu ,  Chung-Te Lin ,  Jerry Chang Jui Kao ,  Sheng-Hsiung Chen ,  Chin-Chou Liu

IPC: H01L27/118 ,  G06F30/398 ,  H01L27/02

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

公开(公告)号：US20220328346A1

公开(公告)日：2022-10-13

申请号：US17346670

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Shyue Lai ,  Gao-Ming Wu ,  Katherine H. Chiang ,  Chung-Te Lin

IPC: H01L21/768 ,  H01L23/522

Abstract: An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.

公开(公告)号：US11437393B2

公开(公告)日：2022-09-06

申请号：US16886732

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H01L27/11558 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11565

Abstract: A memory array includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.

公开(公告)号：US20220278130A1

公开(公告)日：2022-09-01

申请号：US17744212

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Han-Jong Chia ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L27/1159

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.