中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

122 records (took 0.027 seconds)

    3D Semiconductor Package Including Memory Array
    81.
    发明申请
    3D Semiconductor Package Including Memory Array 有权

    公开(公告)号：US20220359486A1

    公开(公告)日：2022-11-10

    申请号：US17814194

    申请日：2022-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Yu-Ming Lin

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L27/1159 ,  H01L27/11597 ,  H01L23/48 ,  H01L29/24

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

    Memory array staircase structure
    82.
    发明授权
    Memory array staircase structure 有权

    公开(公告)号：US11423966B2

    公开(公告)日：2022-08-23

    申请号：US17081380

    申请日：2020-10-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

    IPC: G11C8/14 ,  H01L21/822 ,  H01L21/8239 ,  H01L27/105 ,  H01L27/11597

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

    Memory Array Including Dummy Regions
    84.
    发明申请
    Memory Array Including Dummy Regions 有权

    公开(公告)号：US20210407569A1

    公开(公告)日：2021-12-30

    申请号：US17064279

    申请日：2020-10-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chao-I Wu ,  Sheng-Chen Wang ,  Yu-Ming Lin

    IPC: G11C11/22 ,  H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

    Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

    Epitaxial Structures for Fin-Like Field Effect Transistors
    87.
    发明申请
    Epitaxial Structures for Fin-Like Field Effect Transistors 有权

    公开(公告)号：US20210280696A1

    公开(公告)日：2021-09-09

    申请号：US17324512

    申请日：2021-05-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

    IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/12

    Abstract: A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.

Patent Agency Ranking