公开(公告)号：US11050018B2

公开(公告)日：2021-06-29

申请号：US16664813

申请日：2019-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  David Dai ,  Chung-Ju Lee

IPC: H01L47/00 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L27/24 ,  H01L43/08

Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a first spacer, and a metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The first spacer is disposed along a sidewall of the resistance switching element. The metal-containing compound layer is disposed along a sidewall of the first spacer, in which the first spacer is between the metal-containing compound layer and the resistance switching element.

公开(公告)号：US20210193513A1

公开(公告)日：2021-06-24

申请号：US17012427

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L21/768 ,  H01L23/522

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower conductive structure arranged over a substrate. An etch stop layer is arranged over the lower conductive structure, and a first interconnect dielectric layer is arranged over the etch stop layer. The integrated chip further includes an interconnect via that extends through the first interconnect dielectric layer and the etch stop layer to directly contact the lower conductive structure. A protective layer surrounds outermost sidewalls of the interconnect via.

公开(公告)号：US11018027B2

公开(公告)日：2021-05-25

申请号：US16988609

申请日：2020-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen Tien ,  Wei-Hao Liao ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L21/48 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: An interconnect structure includes a first dielectric layer, an etch stop layer, a conductive via, a conductive line, an intermediate conductive layer, a conductive pillar, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The conductive via is in the first dielectric layer and the etch stop layer. The conductive line is over the conductive via. The intermediate conductive layer is over the conductive line. The conductive pillar is over the intermediate conductive layer. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, and a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

公开(公告)号：US11011421B2

公开(公告)日：2021-05-18

申请号：US17017211

申请日：2020-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Hsu Wu ,  Chien-Hua Huang ,  Chung-Ju Lee ,  Tien-I Bao ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method embodiment includes forming a hard mask over a dielectric layer and forming a first metal line and a second metal line extending through the hard mask into the dielectric layer. The method further includes removing the hard mask, wherein removing the hard mask defines an opening between the first metal line and the second metal line. A liner is then formed over the first metal line, the second metal line, and the dielectric layer, wherein the liner covers sidewalls and a bottom surface of the opening.

公开(公告)号：US10756258B2

公开(公告)日：2020-08-25

申请号：US15860566

申请日：2018-01-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

Abstract: A method for fabricating a memory device includes forming a bottom electrode over a substrate; forming an etch stop layer over and surrounding the bottom electrode; removing at least one portion of the etch stop layer to expose the bottom electrode; forming a stack layer over the bottom electrode and a remaining portion of the etch stop layer, the stack layer comprising a resistance switching layer; and etching the stack layer to form a stack over the bottom electrode, the stack comprising a resistance switching element over the bottom electrode and a top electrode over the resistance switching element, wherein the etch stop layer has a higher etch resistance to the etching than that of the resistance switching element.

公开(公告)号：US20190279896A1

公开(公告)日：2019-09-12

申请号：US16426074

申请日：2019-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

Abstract: Some embodiments relate to a semiconductor device manufacturing process. In the process, a substrate is provided, and a sacrificial layer is formed over the substrate. An opening is patterned through the sacrificial layer, and the opening is filled with conductive material. The sacrificial layer is removed while the conductive material is left in place. A first dielectric layer is formed along sidewalls of the conductive material that was left in place.

公开(公告)号：US10032640B1

公开(公告)日：2018-07-24

申请号：US15628114

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Chien-Hua Huang ,  Chung-Ju Lee ,  Ming-Hui Weng ,  Tzu-Hui Wei

IPC: H01L21/308

Abstract: Methods of fabricating a semiconductor structure using a photoresist cross link process and a photoresist de-cross link process are described. A cross link bottom layer is employed during the fabricating process and the photoresist de-cross link process de-cross links the cross link bottom layer before the bottom layer is removed. The incorporation of the photoresist de-cross link process with the usage of the cross link bottom layer provides a cost effective and low defect level solution to fabricate the semiconductor structure.

公开(公告)号：US20180138076A1

公开(公告)日：2018-05-17

申请号：US15353850

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsin-Ping Chen ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5283

Abstract: A method of forming a semiconductor structure is provided. A conductive layer is formed over a substrate. The conductive layer is selectively etched to form a first conductive portion, a second conductive portion, and a spacing between the first conductive portion and the second conductive portion. A dielectric layer is formed over the first conductive portion, the second conductive portion, and the spacing, such that an air gap is formed in the spacing between the first and second conductive portions and is sealed by the dielectric layer.

公开(公告)号：US09934987B2

公开(公告)日：2018-04-03

申请号：US15149502

申请日：2016-05-09

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chien-Hua Huang ,  Chung-Ju Lee

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/66 ,  H01L21/67 ,  H01L21/311

CPC classification number: H01L21/32134 ,  H01L21/02068 ,  H01L21/31144 ,  H01L21/67023 ,  H01L21/6708 ,  H01L21/67253 ,  H01L22/20

Abstract: A method includes passing a chemical solution through a metal-ion absorber, wherein metal ions in the metal-ion absorber are trapped by the metal-ion absorber. The chemical solution exiting out of the metal-ion absorber is then used to etch a metal-containing region, wherein the metal-containing region includes a metal that is of a same element type as the metal ions.

公开(公告)号：US20170194258A1

公开(公告)日：2017-07-06

申请号：US15463617

申请日：2017-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC: H01L23/528 ,  H01L21/3105 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method for forming an interconnect structure. In some embodiments, the method may be performed by forming an opening within a sacrificial layer. The sacrificial layer is over a substrate. A conductive material is formed within the opening and over the sacrificial layer. The conductive material within the opening defines a conductive body. The conductive material is patterned to define a conductive projection extending outward from the conductive body. The sacrificial layer is removed and a dielectric material is formed surrounding the conductive body and the conductive projection.