公开(公告)号：US11646220B2

公开(公告)日：2023-05-09

申请号：US17650926

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh ,  Jing-Cheng Lin ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/76805 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/76813 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/24 ,  H01L24/27 ,  H01L24/28 ,  H01L24/73 ,  H01L24/82 ,  H01L24/13 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/244 ,  H01L2224/24147 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32145 ,  H01L2224/32265 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/82051 ,  H01L2224/82951 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/83895

Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

公开(公告)号：US11612057B2

公开(公告)日：2023-03-21

申请号：US17815373

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Hsieh ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Li-Han Hsu ,  Wei-Cheng Wu

IPC: H01L23/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

公开(公告)号：US11594520B2

公开(公告)日：2023-02-28

申请号：US17073953

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Cheng-Chieh Hsieh ,  Ming-Yen Chiu

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

公开(公告)号：US20220375767A1

公开(公告)日：2022-11-24

申请号：US17876300

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Der-Chyang Yeh ,  Li-Hsien Huang

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

公开(公告)号：US20220302069A1

公开(公告)日：2022-09-22

申请号：US17833034

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  An-Jhih Su ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L25/10

Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

公开(公告)号：US11342196B2

公开(公告)日：2022-05-24

申请号：US17062803

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Chen-Hua Yu ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  An-Jhih Su ,  Wei-Yu Chen

IPC: H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

公开(公告)号：US20210343626A1

公开(公告)日：2021-11-04

申请号：US17373063

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Ming Shih Yeh

IPC: H01L23/485 ,  H01L25/00 ,  H01L23/528 ,  H01L23/538 ,  H01L23/522 ,  H01L21/683 ,  H01L21/48 ,  H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

公开(公告)号：US20210281037A1

公开(公告)日：2021-09-09

申请号：US17240620

申请日：2021-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chia-Nan Yuan ,  Shih-Guo Shen ,  Der-Chyang Yeh ,  Yu-Hung Lin ,  Ming Shih Yeh

IPC: H01S5/02 ,  H01S5/30 ,  H01S5/026 ,  H01S5/323 ,  H01S5/042 ,  H01S5/0234 ,  H01S5/0237 ,  H01S5/02234

Abstract: In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

公开(公告)号：US20210193618A1

公开(公告)日：2021-06-24

申请号：US17195903

申请日：2021-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

Abstract: An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.

公开(公告)号：US11037819B2

公开(公告)日：2021-06-15

申请号：US16889603

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Der-Chyang Yeh

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L25/10 ,  H05K3/42 ,  H05K3/46 ,  H01L23/498

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.