公开(公告)号：US08395930B2

公开(公告)日：2013-03-12

申请号：US13596154

申请日：2012-08-28

Applicant: Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

Inventor： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

IPC: G11C11/21

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: A method includes applying a first polarity writing voltage pulse to a metal oxide layer to change its resistance state from high to low into a write state, applying a second polarity erasing voltage pulse different from the first polarity to the metal oxide layer to change its resistance state from low to high into an erase state, and applying an initial voltage pulse having the second polarity to the metal oxide layer before first application of the writing voltage pulse, to change an initial resistance value of the metal oxide layer. R0>RH>RL and |V0|>|Ve|≧|Vw| are satisfied where R0, RL, and RH are the resistance values of the initial, write, and erase states, respectively, of the metal oxide layer, and V0, Vw, and Ve are voltage values of the initial, writing, and erasing voltage pulses, respectively.

Abstract translation: 一种方法包括：将第一极性写入电压脉冲施加到金属氧化物层，以将其电阻状态从高变为低电平变为写入状态，将不同于第一极性的第二极性擦除电压脉冲施加到金属氧化物层以改变其电阻 状态从低到高进入擦除状态，以及在首次施加写入电压脉冲之前将具有第二极性的初始电压脉冲施加到金属氧化物层，以改变金属氧化物层的初始电阻值。 R0> RH> RL和| V0 |> | Ve |≥| Vw | 满足R0，RL和RH分别是金属氧化物层的初始，写入和擦除状态的电阻值，V0，Vw和Ve是初始，写入和擦除电压的电压值 脉冲。

公开(公告)号：US20130037775A1

公开(公告)日：2013-02-14

申请号：US13567646

申请日：2012-08-06

Applicant: Satoru Mitani ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Takeshi Takagi

Inventor： Satoru Mitani ,  Yoshihiko Kanzawa ,  Koji Katayama ,  Takeshi Takagi

IPC: H01L45/00 ,  H01L21/02

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9≦x≦1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8≦y≦2.0) are stacked together.

Abstract translation: 本发明的非易失性存储元件包括第一电极（103），第二电极（108） 介于第一电极（103）和第二电极（107）之间的电阻变化层（107），其被配置成响应于施加在电极（103）和（108）之间的电信号可逆地切换电阻值， ，并且电阻变化层（107）具有至少多层结构，其中具有表示为HfO x（0.9＆nlE; x＆nlE; 1.6）的组成的第一含铪层和具有组成的第二含铪层 表示为HfOy（1.8＆nlE; y＆nlE; 2.0）堆叠在一起。

公开(公告)号：US20130010522A1

公开(公告)日：2013-01-10

申请号：US13509616

申请日：2011-10-26

Applicant: Yoshihiko Kanzawa ,  Takeshi Takagi

Inventor： Yoshihiko Kanzawa ,  Takeshi Takagi

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2213/56 ,  G11C2213/76

Abstract: A nonvolatile memory device (800) includes a variable resistance nonvolatile memory element (100) and a control circuit (810). The control circuit (810) determines whether a resistance value of the nonvolatile memory element (100) in a high resistance state is equal to or greater than a predetermined threshold value. Moreover, if the resistance value of the nonvolatile memory element (100) in the high resistance state is smaller than the threshold value, the control circuit (810) applies a first voltage (VL1) to the nonvolatile memory element (100) to change a resistance state of the nonvolatile memory element (100) from the high resistance state to the low resistance state. Moreover, if the resistance value of the nonvolatile memory element (100) in the high resistance state is equal to or greater than the threshold value, the control circuit (810) applies to the nonvolatile memory element (100) a second voltage (VL2) an absolute value of which is smaller an absolute value of the first voltage (VL1) to change the resistance state of the nonvolatile memory element (100) from the high resistance state to the low resistance state.

Abstract translation: 非易失性存储器件（800）包括可变电阻非易失性存储元件（100）和控制电路（810）。 控制电路（810）确定高电阻状态下的非易失性存储元件（100）的电阻值是否等于或大于预定阈值。 此外，如果高电阻状态下的非易失性存储元件（100）的电阻值小于阈值，则控制电路（810）向非易失性存储元件（100）施加第一电压（VL1） 非易失性存储元件（100）从高电阻状态到低电阻状态的电阻状态。 此外，如果高电阻状态下的非易失性存储元件（100）的电阻值为阈值以上，则控制电路（810）向非易失性存储元件（100）施加第二电压（VL2） 其绝对值对于将非易失性存储元件（100）的电阻状态从高电阻状态改变为低电阻状态的第一电压（VL1）的绝对值较小。

公开(公告)号：US08339835B2

公开(公告)日：2012-12-25

申请号：US13000243

申请日：2010-04-22

Applicant: Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

Inventor： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC: G11C11/00

CPC classification number: H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L27/24

Abstract: A nonvolatile memory element includes a current controlling element having a non-linear current-voltage characteristic, a resistance variable element which changes reversibly between a low-resistance state and a high-resistance state in which a resistance value of the resistance variable element is higher than a resistance value of the resistance variable element in the low-resistance state, in response to voltage pulses applied, and a fuse. The current controlling element, the resistance variable element and the fuse are connected in series, and the fuse is configured to be blown when the current controlling element is substantially short-circuited.

Abstract translation: 非易失性存储元件包括具有非线性电流 - 电压特性的电流控制元件，在电阻可变元件的电阻值较高的低电阻状态与高电阻状态之间可逆地改变的电阻可变元件 比电阻可变元件在低电阻状态下的电阻值，响应于施加的电压脉冲和保险丝。 电流控制元件，电阻可变元件和保险丝串联连接，并且当电流控制元件基本上短路时，保险丝被配置为被熔断。

公开(公告)号：US20120319072A1

公开(公告)日：2012-12-20

申请号：US13580401

申请日：2011-02-23

Applicant: Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

Inventor： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC: H01L47/00 ,  H01L21/02

CPC classification number: H01L45/1226 ,  G11C13/0002 ,  G11C2213/77 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1633

Abstract: A manufacturing method for manufacturing, with a simple process, a non-volatile memory apparatus having a stable memory performance includes: (a) forming a stacking-structure body above a substrate by alternately stacking conductive layers comprising a transition metal and interlayer insulating films comprising an insulating material; (b) forming a contact hole penetrating through the stacking-structure body to expose part of each of the conductive layers; (c) forming variable resistance layers by oxidizing the part of each of the conductive layers, the part being exposed in the contact hole, and each of the variable resistance layers having a resistance value that reversibly changes according to an application of an electric signal; and (d) forming a pillar electrode in the contact hole by embedding a conductive material in the contact hole, the pillar electrode being connected to each of the variable resistance layers.

Abstract translation: 一种以简单的工艺制造具有稳定的存储性能的非易失性存储装置的制造方法包括：（a）通过交替堆叠包括过渡金属和层间绝缘膜的导电层，在衬底上形成堆叠结构体，所述导电层包括： 绝缘材料; （b）形成穿过堆叠结构体的接触孔，以暴露出每个导电层的部分; （c）通过氧化每个导电层的一部分形成可变电阻层，该部分暴露在接触孔中，并且每个可变电阻层具有根据电信号的应用可逆地改变的电阻值; 和（d）通过在接触孔中埋设导电材料而在接触孔中形成柱状电极，该柱状电极与各可变电阻层连接。

公开(公告)号：US08320159B2

公开(公告)日：2012-11-27

申请号：US12993706

申请日：2010-03-15

Applicant: Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

Inventor： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

IPC: G11C11/00

CPC classification number: H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode. A first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path (SP) sequentially connecting main terminals of the plurality of memory cells in series. Each of the memory cells is configured such that the control terminal is a part of a first wire (WL) associated with the memory cell or is connected to the first wire associated with the memory cell, the second electrode is a part of a second wire (SL) associated with the memory cell or is connected to the second wire associated with the memory cell; and the first electrode is a part of a series path (SP) associated with the memory cell or is connected to the series path associated with the memory cell.

Abstract translation: 每个存储单元（MC）包括一个晶体管和一个电阻可变元件。 晶体管包括第一主端子，第二主端子和控制端子。 电阻可变元件包括设置在第一电极和第二电极之间的第一电极，第二电极和电阻变化层。 两个相邻存储单元之一的第一主端子连接到另一个存储单元的第二主端子，以形成串联连接多个存储单元的主端子的串行路径（SP）。 每个存储器单元被配置为使得控制端子是与存储器单元相关联的第一布线（WL）的一部分或者连接到与存储单元相关联的第一布线，第二电极是第二布线 （SL），或者连接到与存储器单元相关联的第二线; 并且第一电极是与存储器单元相关联的或连接到与存储器单元相关联的串联路径的串联路径（SP）的一部分。

公开(公告)号：US08295123B2

公开(公告)日：2012-10-23

申请号：US12669174

申请日：2008-07-11

Applicant: Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

Inventor： Takeshi Takagi ,  Takumi Mikawa ,  Koji Arita ,  Mitsuteru Iijima ,  Takashi Okada

IPC: G11C13/00

CPC classification number: H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L45/00

Abstract: In a current rectifying element (10), a barrier height φA of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height φB of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1

Abstract translation: 在电流整流元件（10）中，阻挡层（11）在其厚度方向上的中心区域（14）的阻挡高度＆amp; A被夹在第一电极层（12）和第二电极层（13）之间 ）形成为大于阻挡层（11）和第一电极层（12）之间的界面（17）附近的区域和阻挡层（17）之间的界面（17）的势垒高度B （11）和第二电极层（13）。 阻挡层（11）具有例如阻挡层（11a），（11b）和（11c）的三层结构。 阻挡层（11a），（11b）和（11c）例如由SiNx2，SiNx1和SiNx1（X1

公开(公告)号：US08279658B2

公开(公告)日：2012-10-02

申请号：US12994462

申请日：2010-03-25

Applicant: Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

Inventor： Shunsaku Muraoka ,  Takeshi Takagi ,  Satoru Mitani ,  Koji Katayama

IPC: G11C11/21

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: Applying a writing voltage pulse having a first polarity to a metal oxide layer (3) to change a resistance state of the metal oxide layer (3) from high to low so as to render the resistance state a write state, applying an erasing voltage pulse having a second polarity different from the first polarity to the metal oxide layer (3) to change the resistance state of the metal oxide layer (3) from low to high so as to render the resistance state an erase state, and applying an initial voltage pulse having the second polarity to the metal oxide layer (3) before the applying of a writing voltage pulse is performed for a first time, to change a resistance value of an initial state of the metal oxide layer (3) are included, and R0>RH>RL and |V0|>|Ve|≧|Vw| are satisfied where R0, RL, and RH are the resistance values of the initial, write, and erase states, respectively, of the metal oxide layer (3), and V0, Vw, and Ve are voltage values of the initial, writing, and erasing voltage pulses, respectively.

Abstract translation: 将具有第一极性的写入电压脉冲施加到金属氧化物层（3）以将金属氧化物层（3）的电阻状态从高变为低，以使电阻状态成为写入状态，施加擦除电压脉冲 具有与第一极性不同于金属氧化物层（3）的第二极性，以将金属氧化物层（3）的电阻状态从低到高改变为使得电阻状态为擦除状态，并且施加初始电压 首先执行施加写入电压脉冲之前对金属氧化物层（3）具有第二极性的脉冲，以改变金属氧化物层（3）的初始状态的电阻值，并且R0 > RH> RL和| V0 |> | Ve |≥| Vw | 满足R0，RL和RH分别为金属氧化物层（3）的初始，写入和擦除状态的电阻值，V0，Vw和Ve为初始，写入和写入的电压值， 并分别擦除电压脉冲。

公开(公告)号：US20120094367A1

公开(公告)日：2012-04-19

申请号：US12311175

申请日：2007-09-20

Applicant: Koji Sugiyama ,  Tatsuo Kamata ,  Takeshi Takagi

Inventor： Koji Sugiyama ,  Tatsuo Kamata ,  Takeshi Takagi

IPC: C12M1/40

CPC classification number: G01N33/66 ,  A61B5/14532 ,  G01N33/723 ,  G01N35/026 ,  G01N2030/8822 ,  G01N2800/042

Abstract: The present invention relates to a blood analysis apparatus X for measuring concentrations of glucose and glycohemoglobin in blood. The blood analysis apparatus X is configured to perform the concentration measurement of the glucose and the glycohemoglobin by one sampling of blood 13. The blood analysis apparatus X is preferably configured to simultaneously carry out sample preparations for concentration measurement of the glucose and the glycohemoglobin by one sample preparation. The blood analysis apparatus X may be configured to perform dilution of a blood sample for measuring the glycohemoglobin and dilution of a blood sample for measuring the glucose using the same diluent.

Abstract translation: 血液分析装置技术领域本发明涉及用于测定血液中葡萄糖和糖血红蛋白浓度的血液分析装置X. 血液分析装置X构成为通过血液13的一次取样来进行葡萄糖和糖血红蛋白的浓度测定。血液分析装置X优选同时进行葡萄糖和糖血红蛋白的浓度测定用样品制剂1 样品制备。 血液分析装置X可以被配置为执行用于测量糖血红蛋白的血液样品的稀释和用于使用相同的稀释剂测量葡萄糖的血液样品的稀释。

公开(公告)号：US20120044749A1

公开(公告)日：2012-02-23

申请号：US13266932

申请日：2010-11-02

Applicant: Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Takeshi Takagi ,  Kazuhiko Shimakawa

Inventor： Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Takeshi Takagi ,  Kazuhiko Shimakawa

IPC: G11C11/00 ,  H01L21/8239 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOx and MOy (where x

Abstract translation: 一种可变电阻非易失性存储装置，包括：（i）半导体衬底（301），（ii）具有下电极和上电极（309a，309c）的可变电阻元件（309） 和可变电阻层（309b），其电阻值基于各自具有不同极性的电压信号而被可逆地变化并施加在电极（309a，309c）之间，以及（iii）形成在基板上的MOS晶体管 （301），其中所述可变电阻层（309b）包括：具有组成MOx和MOy（其中x