公开(公告)号：US06239615B1

公开(公告)日：2001-05-29

申请号：US09235371

申请日：1999-01-20

申请人： Tony Ngai ,  Sergey Shumarayev ,  Sammy Cheung ,  Rakesh Patel ,  Vinson Chan

发明人： Tony Ngai ,  Sergey Shumarayev ,  Sammy Cheung ,  Rakesh Patel ,  Vinson Chan

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H01L23/5222 ,  H01L2924/0002 ,  H03K19/1778 ,  H03K19/17792 ,  H03K19/17796 ,  H01L2924/00

摘要： Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

摘要翻译： 为集成电路提供高性能互连的技术将提高整体集成电路性能。 这些技术包括布置，布置和制造信号导体（例如，405,720），使得寄生耦合电容（例如425）最小化并且寄生电阻降低。 这些技术将最小化导体之间串扰噪声的影响，从而提高整体集成电路性能。

公开(公告)号：US10110328B2

公开(公告)日：2018-10-23

申请号：US13446555

申请日：2012-04-13

申请人： Neville Carvalho ,  Tim Tri Hoang ,  Sergey Shumarayev

发明人： Neville Carvalho ,  Tim Tri Hoang ,  Sergey Shumarayev

IPC分类号： G01R35/00 ,  H04B17/21 ,  H04B17/11 ,  G12B13/00

摘要： The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

公开(公告)号：US09559881B2

公开(公告)日：2017-01-31

申请号：US12283652

申请日：2008-09-15

申请人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

发明人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

IPC分类号： H04L7/00 ,  H04B1/38 ,  H04L25/14

CPC分类号： H04L25/14

摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

摘要翻译： 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

公开(公告)号：US09429625B1

公开(公告)日：2016-08-30

申请号：US13475256

申请日：2012-05-18

申请人： Weiqi Ding ,  Sergey Shumarayev

发明人： Weiqi Ding ,  Sergey Shumarayev

IPC分类号： G01R31/00 ,  G01R31/319 ,  G01R31/40

CPC分类号： G01R31/31924 ,  G01R31/3167 ,  G01R31/40

摘要： An analog test network includes a conductor. The conductor is coupled to provide a first analog signal from a circuit under test to an analog-to-digital converter circuit. The analog-to-digital converter circuit is operable to generate a first digital signal based on the first analog signal. A control circuit is operable to generate a second digital signal based on the first digital signal. A digital-to-analog converter circuit is operable to generate a second analog signal based on the second digital signal. The conductor is coupled to provide the second analog signal from the digital-to-analog converter circuit to the circuit under test.

摘要翻译： 模拟测试网络包括导体。 导体被耦合以从被测电路提供到模拟 - 数字转换器电路的第一模拟信号。 模数转换器电路可操作以基于第一模拟信号产生第一数字信号。 控制电路可操作以基于第一数字信号产生第二数字信号。 数模转换器电路可操作以基于第二数字信号产生第二模拟信号。 导体被耦合以将第二模拟信号从数模转换器电路提供给被测电路。

公开(公告)号：US08976804B1

公开(公告)日：2015-03-10

申请号：US13041764

申请日：2011-03-07

申请人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H04L12/66

CPC分类号： H03K19/17744

摘要： In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

摘要翻译： 在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。 对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。 对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。 对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。 对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。 片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

公开(公告)号：US08723572B1

公开(公告)日：2014-05-13

申请号：US13436385

申请日：2012-03-30

申请人： Weiqi Ding ,  Sergey Shumarayev

发明人： Weiqi Ding ,  Sergey Shumarayev

IPC分类号： H03K5/12

CPC分类号： H03K5/1565

摘要： One embodiment relates a method of correcting skew and/or duty cycle distortion in a differential signal using a transmitter buffer circuit. Skew and/or duty cycle distortion may be detected in the differential signal. Delay times for at least two variable-delay buffer circuits are adjusted. The variable-delay buffer circuits may have outputs coupled to control gates of pull-up and pull-down transistors coupled to one or more output nodes of the transmitter buffer circuit. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及使用发射机缓冲电路来校正差分信号中的偏移和/或占空比失真的方法。 可以在差分信号中检测到偏斜和/或占空比失真。 调整至少两个可变延迟缓冲电路的延迟时间。 可变延迟缓冲电路可以具有耦合到耦合到发送器缓冲电路的一个或多个输出节点的上拉和下拉晶体管的控制栅极的输出。 还公开了其它实施例，方面和特征。

公开(公告)号：US08705602B1

公开(公告)日：2014-04-22

申请号：US12580587

申请日：2009-10-16

申请人： Weiqi Ding ,  Mengchi Liu ,  Mingde Pan ,  Thungoc M. Tran ,  Sergey Shumarayev

发明人： Weiqi Ding ,  Mengchi Liu ,  Mingde Pan ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC分类号： H03H7/30 ,  H03H7/40

CPC分类号： H04L25/03038 ,  H04L25/03343

摘要： Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).

摘要翻译： 例如，用于串行数字数据信号的发射机均衡器电路包括用于输出通过延迟线电路传播的信号的多个不同延迟版本的抽头延迟线电路。 均衡器电路还包括多个电流数模转换器（“DAC”）。 均衡器电路还包括可控（例如，可编程）路由电路，用于可选地将信号的延迟版本路由到各​​种DAC。 各种DAC所使用的电流强度也优选是可控的（例如，可编程的）。

公开(公告)号：US08653853B1

公开(公告)日：2014-02-18

申请号：US11618828

申请日：2006-12-31

申请人： Sergey Shumarayev ,  Tim Tri Hoang ,  Lawrence David Smith

发明人： Sergey Shumarayev ,  Tim Tri Hoang ,  Lawrence David Smith

IPC分类号： H03K19/0175

CPC分类号： H03K19/0175 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/17744 ,  H03K19/17784 ,  H03K19/17788

摘要： Techniques are provided for transmitting signals through a differential interface between circuits in different power supply domains. A driver circuit in a first power supply domain converts single-ended signals into differential signals. The driver circuit then transmits the differential signals to a receiver circuit in a second power supply domain. The receiver circuit converts the differential signals back into single-ended signals for transmission to circuit elements in the second power supply domain. The differential interface reduces the transmission of noise between circuit elements in the first power supply domain and circuit elements in the second power supply domain.

摘要翻译： 提供了用于通过不同电源域中的电路之间的差分接口传输信号的技术。 第一电源域中的驱动电路将单端信号转换成差分信号。 然后，驱动器电路将差分信号发送到第二电源域中的接收器电路。 接收器电路将差分信号转换回单端信号以传输到第二电源域中的电路元件。 差分接口减少了第一电源域中的电路元件与第二电源域中的电路元件之间的噪声传输。

公开(公告)号：US08537956B1

公开(公告)日：2013-09-17

申请号：US12954514

申请日：2010-11-24

申请人： Tien Duc Pham ,  Leon Zheng ,  Sergey Shumarayev ,  Zhi Y. Wong ,  Paul B. Ekas

发明人： Tien Duc Pham ,  Leon Zheng ,  Sergey Shumarayev ,  Zhi Y. Wong ,  Paul B. Ekas

IPC分类号： H03D3/24

CPC分类号： H03L7/0802 ,  H03L7/1976 ,  H04J3/047 ,  H04J3/062

摘要： A demultiplexer circuit separates input data having different data rates into output data. A phase-locked loop circuit generates first clock signals having average frequencies that are based on a frequency of a second clock signal times a fractional, non-integer number. A serializer circuit serializes a set of the output data to generate serial data signals in response to one of the first clock signals generated by the phase-locked loop circuit.

摘要翻译： 解复用器电路将具有不同数据速率的输入数据分离成输出数据。 锁相环电路产生具有基于第二时钟信号的频率的平均频率乘以分数非整数的第一时钟信号。 串行器电路串行化一组输出数据以响应于由锁相环电路产生的第一时钟信号之一产生串行数据信号。

公开(公告)号：US08464088B1

公开(公告)日：2013-06-11

申请号：US12915794

申请日：2010-10-29

申请人： Toan Thanh Nguyen ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Thungoc M. Tran

发明人： Toan Thanh Nguyen ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Thungoc M. Tran

IPC分类号： G06F1/04

CPC分类号： G06F1/04 ,  G06F1/10

摘要： Various methods and structures related to clock distribution for flexible channel bonding are disclosed. One embodiment provides a clock network in physical media attachment (“PMA”) circuitry, a specific type or portion of system interconnect circuitry, arranged in pairs of channel groups. In one embodiment, clock generation circuitry blocks (“CGBs”) in each pair of channel groups receives outputs of multiple phased locked loop circuits (“PLLs”) which can be selectively utilized by the CGBs to generate PMA clock signals. In another embodiment, the CGBs can also select output of a clock data recovery (“CDR”)/transmit PLL circuitry block in one of the channels of a channel group of the pair of channel groups. In one embodiment, first groups of connection lines couple circuitry in a channel group pair such that a designated CGB in each channel group pair can provide clock signals to one or more of the channels in the channel group pair. In one embodiment, second groups of connection lines connect channels in one channel group pair to channels in other channel group pairs such that one or more channels across the channel group pairs can receive a clock signal generated by a CGB in a designated channel. These and other embodiments are described more fully in the disclosure.

摘要翻译： 公开了与用于柔性通道结合的时钟分配有关的各种方法和结构。 一个实施例提供物理介质连接（“PMA”）电路中的时钟网络，系统互连电路的特定类型或部分，被布置成成对的信道组。 在一个实施例中，每对信道组中的时钟产生电路块（“CGB”）接收多个锁相环电路（“PLL”）的输出，这些电路可被CGB选择性地用于产生PMA时钟信号。 在另一个实施例中，CGB还可以在一对信道组的信道组的信道之一中选择时钟数据恢复（“CDR”）/发送PLL电路块的输出。 在一个实施例中，第一组连接线将信道组对中的电路耦合，使得每个信道组对中的指定CGB可以向信道组对中的一个或多个信道提供时钟信号。 在一个实施例中，第二组连接线将一个信道组对中的信道与其它信道组对中的信道相连，使得跨信道组对的一个或多个信道可以接收由指定信道中的CGB产生的时钟信号。 在本公开中更全面地描述了这些和其它实施例。