公开(公告)号：US08653853B1

公开(公告)日：2014-02-18

申请号：US11618828

申请日：2006-12-31

申请人： Sergey Shumarayev ,  Tim Tri Hoang ,  Lawrence David Smith

发明人： Sergey Shumarayev ,  Tim Tri Hoang ,  Lawrence David Smith

IPC分类号： H03K19/0175

CPC分类号： H03K19/0175 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/17744 ,  H03K19/17784 ,  H03K19/17788

摘要： Techniques are provided for transmitting signals through a differential interface between circuits in different power supply domains. A driver circuit in a first power supply domain converts single-ended signals into differential signals. The driver circuit then transmits the differential signals to a receiver circuit in a second power supply domain. The receiver circuit converts the differential signals back into single-ended signals for transmission to circuit elements in the second power supply domain. The differential interface reduces the transmission of noise between circuit elements in the first power supply domain and circuit elements in the second power supply domain.

摘要翻译： 提供了用于通过不同电源域中的电路之间的差分接口传输信号的技术。 第一电源域中的驱动电路将单端信号转换成差分信号。 然后，驱动器电路将差分信号发送到第二电源域中的接收器电路。 接收器电路将差分信号转换回单端信号以传输到第二电源域中的电路元件。 差分接口减少了第一电源域中的电路元件与第二电源域中的电路元件之间的噪声传输。

公开(公告)号：US08811555B2

公开(公告)日：2014-08-19

申请号：US12700433

申请日：2010-02-04

申请人： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

发明人： Kazi Asaduzzaman ,  Tim Tri Hoang ,  Tin H. Lai ,  Shou-Po Shih ,  Sergey Shumarayev

IPC分类号： H04L7/00 ,  H03L7/081 ,  H04L7/033 ,  H03L7/08

CPC分类号： H03L7/08 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0898 ,  H03L7/099 ,  H03L7/183 ,  H04L7/0337

摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).

摘要翻译： 集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。 由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。 响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。

公开(公告)号：US08416001B2

公开(公告)日：2013-04-09

申请号：US13083431

申请日：2011-04-08

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Yanjing Ke

IPC分类号： H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC分类号： H03K5/1565 ,  H03K3/017 ,  H03K5/12 ,  H03M9/00

摘要： A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

摘要翻译： 发射机电路可操作以响应于第一周期性信号提供输出信号。 多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。 多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。 采样器电路可操作以在第一操作阶段产生所选信号的第一采样。 采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。 占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

公开(公告)号：US08290750B1

公开(公告)日：2012-10-16

申请号：US13036437

申请日：2011-02-28

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang ,  Weiqi Ding

IPC分类号： H03F1/26

CPC分类号： H03K5/19 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778

摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.

摘要翻译： 串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。 可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。 用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。 因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。 可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。 该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

公开(公告)号：US07860203B1

公开(公告)日：2010-12-28

申请号：US11725653

申请日：2007-03-19

申请人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

发明人： Sergey Shumarayev ,  Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

摘要： A programmable logic device integrated circuit (“PLD”) includes high-speed serial interface (“HSSI”) circuitry in addition to programmable logic circuitry. The HSSI circuitry includes multiple channels of nominal data-handling circuitry (typically including clock and data recovery (“CDR”) circuitry), and at least one channel of nominal clock management unit (“CMU”) circuitry (typically including phase-locked loop (“PLL”) circuitry or the like). To increase the flexibility with which the channels can be used, the nominal data-handling channels are equipped to alternatively perform CMU-type functions, and the nominal CMU channel is equipped to alternatively perform data-handling functions.

摘要翻译： 可编程逻辑器件集成电路（“PLD”）除了可编程逻辑电路之外还包括高速串行接口（“HSSI”）电路。 HSSI电路包括多个标称数据处理电路（通常包括时钟和数据恢复（“CDR”）电路）的通道，以及标称时钟管理单元（“CMU”）电路的至少一个通道（通常包括锁相环 （“PLL”）电路等）。 为了增加可以使用信道的灵活性，标称数据处理信道被配备为交替执行CMU类型功能，并且标称CMU信道被配备为备选地执行数据处理功能。

公开(公告)号：US07619451B1

公开(公告)日：2009-11-17

申请号：US11670971

申请日：2007-02-03

申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Kazi Asaduzzaman ,  Wanli Chang ,  Mian Z. Smith ,  Kang-Wei Lai ,  Leon Zheng

发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Kazi Asaduzzaman ,  Wanli Chang ,  Mian Z. Smith ,  Kang-Wei Lai ,  Leon Zheng

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  G06F1/12 ,  H03L7/081 ,  H03L7/0812

摘要： Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.

摘要翻译： 提供了用于补偿由集成电路上的锁相环和延迟锁定环路产生的时钟信号中的相位和定时延迟的技术。 耦合在锁定电路的反馈回路中的电路元件可以补偿输入引脚和输出引脚之间的定时和相位延迟。 耦合在锁定电路的反馈环路中的其它电路元件可以补偿输入引脚和目的地电路元件之间的延迟。 耦合在锁定电路的输入参考路径中的其他电路元件保留输入时钟和输入数据信号之间的定时关系。 在目的地电路元件处接收的时钟信号和数据信号在输入引脚的输入时钟和输入数据信号之间具有相同的相位和定时关系。

公开(公告)号：US20090011716A1

公开(公告)日：2009-01-08

申请号：US11773234

申请日：2007-07-03

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H04Q7/20

CPC分类号： H04L25/45

摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US07429897B1

公开(公告)日：2008-09-30

申请号：US11514489

申请日：2006-08-31

申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

IPC分类号： H03B5/08

CPC分类号： H03K3/0315 ,  H03K5/133 ,  H03K2005/00202 ,  H03L7/0995 ,  H03L2207/06

摘要： Voltage controlled oscillator (VCO) circuitry with low phase noise and a wide range of operating frequencies is presented. The VCO circuitry includes circuitry with two or more VCO sub-circuits, each sub-circuit being optimized to produce output clock signals with low phase noise and with frequencies in a different range. Sub-circuits with gear inputs may be operative to produce output clock signals in a lower range of frequencies, while sub-circuits optimized for high speed operation may be used to produce output signals in a higher range of frequencies. A control circuit may be used to produce a control signal coupled to all sub-circuits. The control signal may set the operating frequency of the sub-circuits.

摘要翻译： 介绍了具有低相位噪声和宽范围工作频率的压控振荡器（VCO）电路。 VCO电路包括具有两个或多个VCO子电路的电路，每个子电路被优化以产生具有低相位噪声和频率在不同范围内的输出时钟信号。 具有齿轮输入的子电路可以用于产生在较低频率范围内的输出时钟信号，而针对高速操作优化的子电路可用于产生较高频率范围内的输出信号。 控制电路可用于产生耦合到所有子电路的控制信号。 控制信号可以设定子电路的工作频率。

公开(公告)号：US08619931B1

公开(公告)日：2013-12-31

申请号：US12622152

申请日：2009-11-19

申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Vinh Van Ho ,  Leon Zheng

发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Vinh Van Ho ,  Leon Zheng

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H04L7/002

摘要： Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.

摘要翻译： 提供了具有能够在没有专用锁相环电路的情况下能够进行高速（例如，1Gbps）操作的收发器的集成电路。 一个这样的集成电路设备可以包括能够发送和接收大约1Gbps或更大的串行信号的一个或多个收发器，以及能够向一个或多个收发器提供多相时钟信号的多用途锁相环。

公开(公告)号：US08406258B1

公开(公告)日：2013-03-26

申请号：US12752984

申请日：2010-04-01

申请人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

发明人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

IPC分类号： H04J3/06

CPC分类号： H03M9/00 ,  H03K19/1776 ,  H04J3/047 ,  H04J3/0685

摘要： One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.

摘要翻译： 一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。 每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。 第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号 基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。 时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。 还公开了其它实施例和特征。