公开(公告)号：US07821343B1

公开(公告)日：2010-10-26

申请号：US12229813

申请日：2008-08-27

申请人： Wilson Wong ,  Sergey Shumarayev ,  Allen Chan ,  Weiqi Ding

发明人： Wilson Wong ,  Sergey Shumarayev ,  Allen Chan ,  Weiqi Ding

IPC分类号： H03L7/00

CPC分类号： H03L7/23

摘要： A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL. In wide range mode, a wider frequency range is desirable. On the other hand, in low jitter mode, a low jitter is desirable.

摘要翻译： 描述了包括耦合到第一PLL的第一锁相环（PLL）和第二PLL的发射机。 在一个实现中，第一PLL是电感 - 电容（LC）型PLL，第二PLL是环型PLL。 此外，在一个实施例中，发射机还包括耦合到第一和第二PLL的PLL选择多路复用器，其中PLL选择多路复用器接收第一PLL的输出和第二PLL的输出，并输出第一PLL的输出 或第二PLL的输出。 在一个实现中，用于控制PLL选择多路复用器的选择的控制信号在运行时可编程。 在一个实现中，本发明的发射机还包括耦合到PLL选择多路复用器的时钟产生模块，耦合到时钟产生模块的串行器模块和耦合到串行器模块的发送驱动器模块。 在一个实施例中，发射驱动器块仅包括一个抽头前驱动器和仅一个主抽头预驱动器。 本发明的发射机能够通过选择适当的PLL在宽范围模式或低抖动模式下工作。 在宽范围模式下，需要较宽的频率范围。 另一方面，在低抖动模式中，需要低抖动。

公开(公告)号：US07773668B1

公开(公告)日：2010-08-10

申请号：US10762864

申请日：2004-01-21

申请人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Rakesh Patel

发明人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Rakesh Patel

IPC分类号： H03H7/30 ,  H03H7/40

CPC分类号： H04L25/03044 ,  H04L2025/03356 ,  H04L2025/03579 ,  H04L2025/03783

摘要： A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.

摘要翻译： 可编程逻辑器件设置有可在一个或多个方面可编程的自适应均衡电路。 均衡电路的可编程方面的示例是（1）使用的抽头数量，（2）是否使用整数或分数间隔抽头，（3）在系数值的计算中使用什么起始值，（4）是否 （5）是否使用决策导向算法或使用训练模式生成错误信号，（6）使用何种训练模式（如果有的话）和/ 或者（7）要被均衡的信号的位周期内的采样点的位置。

公开(公告)号：US20100090774A1

公开(公告)日：2010-04-15

申请号：US12277810

申请日：2008-11-25

申请人： Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

发明人： Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

IPC分类号： H03B5/18

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

摘要： An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

摘要翻译： 振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。 振荡器电路还包括第二导电层中的变容二极管，电容器和选项导体。 选项导体形成晶体管之一和电容器或变容二极管之间的连接的至少一部分。

公开(公告)号：US07688106B1

公开(公告)日：2010-03-30

申请号：US11712609

申请日：2007-02-27

申请人： Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat ,  Wilson Wong

发明人： Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat ,  Wilson Wong

IPC分类号： H03K19/173

CPC分类号： H03K19/17744

摘要： High-speed serial interface (“HSSI”) transceiver circuitry (e.g., on a programmable logic device (“PLD”) integrated circuit) includes input buffer circuitry with adaptive equalization capability. The transceiver circuitry also includes an output driver, which may include pre-emphasis capability (preferably controllably settable). Selectively usable loop-back circuitry is provided for allowing the output signal of the input buffer to be applied substantially directly to the output driver. The loop-back circuitry may include a loop-back driver, which may be turned on substantially only when needed for loop-back operations.

摘要翻译： 高速串行接口（“HSSI”）收发器电路（例如，在可编程逻辑器件（“PLD”）集成电路上）包括具有自适应均衡能力的输入缓冲器电路。 收发器电路还包括输出驱动器，其可以包括预加重功能（优选可控地设置）。 提供了可选择的环回电路，用于使输入缓冲器的输出信号基本上直接施加到输出驱动器。 环回电路可以包括环回驱动器，其可以基本上仅在环回操作需要时被导通。

公开(公告)号：US07659745B1

公开(公告)日：2010-02-09

申请号：US12218688

申请日：2008-07-16

申请人： Wilson Wong ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Wilson Wong ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H03K19/0175 ,  H03K5/00 ,  G06F7/38

CPC分类号： H03K19/17744

摘要： A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.

摘要翻译： 可编程逻辑器件（“PLD”）包括用于在几个方面中的任何一个中可选地且可变地修改输入信号的特性的电路。 这样的修改的示例包括将信号AC耦合到PLD中，对信号进行低通滤波（具有可选择的低通滤波器转角频率），移位输入信号的公共电压，和/或使输入信号经受可选择量的 衰减。

公开(公告)号：US07590207B1

公开(公告)日：2009-09-15

申请号：US11256346

申请日：2005-10-20

申请人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

发明人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

摘要： A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.

摘要翻译： 用于可编程逻辑器件的串行接口可以用作传统的高速四边形接口，但是也允许单独的通道（如果不另外使用）被可编程地配置为环路电路（例如，锁相环） 。 这是通过禁用通道中的时钟数据恢复电路的数据循环来实现的，并且重新配置参考环路以用作循环电路。 此外，不是提供具有四个通道的高速四边形接口和一个或多个时钟管理单元（CMU），而是可以提供具有五个或更多个通道的更灵活的接口，并且当希望将接口用作 高速四通道接口，一个或多个通道可以配置为循环电路，用作CMU。

公开(公告)号：US07555087B1

公开(公告)日：2009-06-30

申请号：US12027909

申请日：2008-02-07

申请人： Kazi Asaduzzaman ,  Wilson Wong

发明人： Kazi Asaduzzaman ,  Wilson Wong

IPC分类号： H04L7/02

CPC分类号： H04L7/0338 ,  H03L7/0807 ,  H03L7/087

摘要： Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.

摘要翻译： 可以为时钟数据恢复（CDR）电路提供动态支持，以改变由不同协议的接口引起的数据速率。 以参考时钟模式和数据模式工作的CDR电路可以由两个控制信号控制，这两个信号指示CDR电路在参考时钟模式和数据模式之间自动切换，仅在参考时钟模式下工作，或仅在 数据模式。 控制信号可由可编程逻辑器件（PLD），PLD外部电路或用户输入设置。 也可以在CDR电路中提供动态可调节的百万分之一（PPM）检测器，以在参考时钟模式完成期间处理数据时发出信号。

公开(公告)号：US20090141787A1

公开(公告)日：2009-06-04

申请号：US12358459

申请日：2009-01-23

申请人： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

发明人： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

IPC分类号： H04L27/01

CPC分类号： H04L1/205 ,  H04B17/21 ,  H04B17/24 ,  H04B17/309 ,  H04L25/03006

摘要： A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e.g., equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.

摘要翻译： 系统包括经由用于从发射机向接收机发送高速数据信号的传输介质连接到可编程接收机设备（例如，另一个PLD）的可编程发射机设备（例如，PLD）。 在测试操作模式期间，发射机和接收机之间的低速通信链路允许这些设备一起工作，以经由传输介质从发射机向接收机发送具有已知特性的测试信号，以分析由 接收器，并且至少部分地补偿由接收器接收的测试信号中的损耗，系统的至少一些方面（例如，接收机中的均衡器电路）。

公开(公告)号：US07417462B1

公开(公告)日：2008-08-26

申请号：US11726174

申请日：2007-03-20

申请人： Wilson Wong ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Wilson Wong ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H03K19/0175 ,  H03K5/00 ,  G06F7/38

CPC分类号： H03K19/17744

摘要： A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.

摘要翻译： 可编程逻辑器件（“PLD”）包括用于在几个方面中的任何一个中可选地且可变地修改输入信号的特性的电路。 这样的修改的示例包括将信号AC耦合到PLD中，对信号进行低通滤波（具有可选择的低通滤波器转角频率），移位输入信号的公共电压，和/或使输入信号经受可选择量的 衰减。

公开(公告)号：US07397270B1

公开(公告)日：2008-07-08

申请号：US11138919

申请日：2005-05-25

申请人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

发明人： Mei Luo ,  Sergey Shumarayev ,  Wilson Wong ,  Chong H. Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/00369 ,  H03K19/01812 ,  H03K19/01837 ,  H03K19/018514 ,  H03K19/018585

摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

摘要翻译： 使用动态可调差分输出驱动器提供系统和方法。 诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。 可以调整输出驱动器的峰峰值输出电压和共模电压。 动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。 基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。