公开(公告)号：US08441058B2

公开(公告)日：2013-05-14

申请号：US13180361

申请日：2011-07-11

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： H01L29/788

CPC分类号： H01L21/762 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.

公开(公告)号：US20130107602A1

公开(公告)日：2013-05-02

申请号：US13601531

申请日：2012-08-31

申请人： Sang Hyun OH ,  Seiichi Aritome ,  Sang Bum LEE

发明人： Sang Hyun OH ,  Seiichi Aritome ,  Sang Bum LEE

IPC分类号： H01L27/088 ,  H01L21/336 ,  G11C5/02

CPC分类号： H01L27/11556 ,  G11C16/0408 ,  G11C16/14 ,  H01L21/8221 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

摘要： A three-dimensional (3-D) nonvolatile memory device includes a channel layer protruded from a substrate, a plurality of memory cells stacked along the channel layer, a source line coupled to the end of one side of the channel layer, a bit line coupled to the end of the other side of the channel layer, a first junction interposed between the end of one side of the channel layer and the source line and configured to have a P type impurity doped therein, and a second junction interposed between the end of the other side of the channel layer and the bit line and configured to have an N type impurity doped therein.

摘要翻译： 三维（3-D）非易失性存储器件包括从衬底突出的沟道层，沿着沟道层堆叠的多个存储单元，耦合到沟道层一侧的端部的源极线，位线 耦合到沟道层的另一侧的端部，插入在沟道层的一侧的端部和源极线之间并且被配置为在其中掺杂有P型杂质的第一结，以及插入在端部之间的第二结 的沟道层的另一侧和位线，并且被配置为在其中掺杂有N型杂质。

公开(公告)号：US08339858B2

公开(公告)日：2012-12-25

申请号：US13285697

申请日：2011-10-31

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

摘要： Memory devices and methods of programming memory cells including selecting a voltage to apply to a control gate of the memory cell during programming of a data value of a sense amplifier to the memory cell in response to at least a data value contained in a data latch that is in communication with the sense amplifier.

公开(公告)号：US20120241840A1

公开(公告)日：2012-09-27

申请号：US13402989

申请日：2012-02-23

申请人： Nam-Jae Lee ,  Seiichi Aritome

发明人： Nam-Jae Lee ,  Seiichi Aritome

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L21/76224 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： A nonvolatile memory device includes a substrate having active regions that are defined by an isolation layer and that have first sidewalls extending upward from the isolation layer, floating gates adjoining the first sidewalls of the active regions with a tunnel dielectric layer interposed between the active regions and the floating gates and extending upward from the substrate, an intergate dielectric layer disposed over the floating gates, and control gates disposed over the intergate dielectric layer.

摘要翻译： 非易失性存储器件包括具有由隔离层限定的并且具有从隔离层向上延伸的第一侧壁的有源区的衬底，与有源区相邻的浮动栅极与介于有源区之间的隧道介电层和 浮置栅极并从衬底向上延伸，布置在浮置栅极上的隔间介电层以及设置在栅极间介电层上的控制栅极。

公开(公告)号：US08264879B2

公开(公告)日：2012-09-11

申请号：US12948469

申请日：2010-11-17

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/349 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

摘要： Methods, devices, modules, and systems for operating memory cells are taught. A method for operating memory cells includes programming at least one of the memory cells to one of a number of states. Operating memory cells also includes programming at least another one of the memory cells, which is adjacent to the programmed at least one of the memory cells, to one of a different number of states. Operating memory cells also includes sensing non-erased states of the memory cells using at least one common voltage level.

摘要翻译： 教授了用于操作存储器单元的方法，设备，模块和系统。 用于操作存储器单元的方法包括将至少一个存储器单元编程为多个状态之一。 操作存储器单元还包括将与编程的至少一个存储器单元相邻的存储单元中的至少另一个存储器编程为不同数量的状态之一。 操作存储单元还包括使用至少一个公共电压电平来感测存储器单元的未擦除状态。

公开(公告)号：US08199572B2

公开(公告)日：2012-06-12

申请号：US13186172

申请日：2011-07-19

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C5/04 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641

摘要： Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells.

摘要翻译： 存储器阵列和操作这样的存储器阵列的方法被描述为具有作为单电平单元操作的存储单元，该存储单元被插入并耦合到选择栅极和作为多电平存储单元操作的存储单元。 在一些实施例中，存储器阵列被描述为包括与作为单级存储器单元操作的多个存储器单元和作为多级存储器单元操作的多个存储单元串联耦合的多个选择栅极，其中第一选择栅极为 直接耦合到第一存储器单元，该第一存储器单元被操作为插入在第一选择栅极之间并耦合到第一选择栅极的单层存储器单元，以及作为多级存储单元操作的连续数量的存储单元。

公开(公告)号：US08163610B2

公开(公告)日：2012-04-24

申请号：US13117364

申请日：2011-05-27

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： H01L29/42336 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/7881

摘要： Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality fins is formed, the fins are isotropically etched to reduce a width of the fins and to round an upper surface of the fins. A first dielectric layer is formed overlying the isotropically etched fins. A first conductive layer is formed overlying the first dielectric layer. A second dielectric layer is formed overlying the first conductive layer. A second conductive layer is formed overlying the second dielectric layer.

摘要翻译： 提供了方法和装置。 对于一个实施例，在基板中形成多个散热片，使得散热片从基板突出。 在形成多个翅片之后，翅片被各向同性地蚀刻以减小散热片的宽度并绕散热片的上表面。 形成覆盖各向同性蚀刻的散热片的第一电介质层。 第一导电层形成在第一介电层上。 形成覆盖在第一导电层上的第二电介质层。 第二导电层形成在第二介电层上。

公开(公告)号：US08144519B2

公开(公告)日：2012-03-27

申请号：US12973110

申请日：2010-12-20

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/06

CPC分类号： G11C16/3454

摘要： An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and increases for each word line that is verified up to a maximum verify voltage. A second verify read operation is then performed after the program/verify operation. The second verify read operation uses a verify voltage that is substantially close to the maximum verify voltage used during the program/verify step.

摘要翻译： 在每个编程脉冲之后执行初始验证读操作。 验证电压从第一个字线的初始验证电压开始，并且每个被验证到最大验证电压的字线增加。 然后在程序/验证操作之后执行第二验证读操作。 第二次验证读取操作使用基本上接近程序/验证步骤期间使用的最大验证电压的验证电压。

公开(公告)号：US08120954B2

公开(公告)日：2012-02-21

申请号：US12833562

申请日：2010-07-09

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C11/5635 ,  G11C16/0483 ,  G11C16/107 ,  G11C16/3404 ,  G11C16/3409

摘要： Methods, apparatus, and systems may operate to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. An example of applying such a pre-programming operation involves applying a series of voltage pulses to the plurality of multiple level memory cells, verifying a charge stored in the plurality of multiple level memory cells, and erasing the plurality of multiple level memory cells of the memory block based on a result from verifying the charge stored in the plurality of multiple level memory cells.

摘要翻译： 方法，装置和系统可以操作以在存储器件的多个多级存储器单元上执行预编程操作。 应用这样的预编程操作的示例包括将一系列电压脉冲施加到多个多级存储器单元，验证存储在多个多级存储器单元中的电荷，以及擦除多个多级存储器单元中的多个多级存储器单元 存储块基于验证存储在多个多级存储器单元中的电荷的结果。

公开(公告)号：US07995391B2

公开(公告)日：2011-08-09

申请号：US12868245

申请日：2010-08-25

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.

摘要翻译： 描述与非易失性存储器单元相关联的多个选择门。 各种实施例包括多个选择栅极结构，工艺和操作及其对存储器件，模块和系统的适用性。 在一个实施例中描述了存储器阵列。 存储器阵列包括多个与多个非易失性存储器单元串联耦合的选择栅极。 第一选择栅极包括电连接在一起的控制栅极和浮置栅极，第二选择栅极包括由电介质层电隔离的控制栅极和浮置栅极。