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公开(公告)号：US08482997B2
公开(公告)日：2013-07-09
申请号：US13366329
申请日：2012-02-05
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
摘要翻译： 实现了高度可靠的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。
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公开(公告)号：US08184463B2
公开(公告)日：2012-05-22
申请号：US12636758
申请日：2009-12-13
CPC分类号： H01L25/0657 , G11C5/02 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/13091 , H01L2924/15311 , H01L2924/00 , H01L2224/05599
摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.
摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。
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83.发明授权Semiconductor memory device having a sense amplifier circuit with decreased offset 有权半导体存储器件具有具有减小的偏移的读出放大器电路公开(公告)号：US07876627B2
公开(公告)日：2011-01-25
申请号：US11969223
申请日：2008-01-03
申请人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
发明人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , H01L27/10897
摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.
摘要翻译： 具有高集成度，低功耗和高操作速度的半导体存储器件。 存储器件包括具有多个下拉电路和上拉电路的读出放大器电路。 构成多个下拉电路中的一个的晶体管具有比构成其它下拉电路的晶体管的常数更大的常数，例如沟道长度和沟道宽度。 具有较大恒定晶体管的下拉电路比另一个下拉电路和上拉电路更早启动，这些电路被激活以进行读取。 数据线和较早驱动的下拉电路由NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制下拉电路的激活或失活。
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公开(公告)号：US07843250B2
公开(公告)日：2010-11-30
申请号：US12686430
申请日：2010-01-13
IPC分类号： H03K3/01
CPC分类号： G11C5/146 , G11C11/401 , G11C11/4074 , G11C29/02 , G11C29/026 , G11C29/028 , H01L2924/0002 , H01L2924/00
摘要： A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.
摘要翻译： 一种防止工作速度降低的基板电压控制技术，并且相对于低电压使用而抑制由于阈值电压较低导致的漏电流。 由于通过多个复制MOS晶体管检测阈值电压的中心值，并且控制衬底电压以控制阈值电压的中心值，从而可以满足操作速度的下限和上限 整个芯片的漏电流。 另一方面，在芯片工作期间动态地控制衬底电压，从而可以在芯片工作时降低阈值电压的中心值以提高速度，并且增加阈值电压的中心值 芯片运行后降低整个芯片的漏电流。
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公开(公告)号：US07659769B2
公开(公告)日：2010-02-09
申请号：US11771779
申请日：2007-06-29
IPC分类号： G05F1/10
CPC分类号： G11C5/146 , G11C11/401 , G11C11/4074 , G11C29/02 , G11C29/026 , G11C29/028 , H01L2924/0002 , H01L2924/00
摘要： A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.
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公开(公告)号：US07609572B2
公开(公告)日：2009-10-27
申请号：US11963831
申请日：2007-12-22
申请人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
发明人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/08 , G11C2207/005
摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.
摘要翻译： 在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。 通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低 感觉速度增加。 因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。
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公开(公告)号：US20090129173A1
公开(公告)日：2009-05-21
申请号：US12269098
申请日：2008-11-12
申请人： Shinya KAJIYAMA , Yutaka Shinagawa , Makoto Mizuno , Hideo Kasai , Takao Watanabe , Riichiro Takemura , Tomonori Sekiguchi
发明人： Shinya KAJIYAMA , Yutaka Shinagawa , Makoto Mizuno , Hideo Kasai , Takao Watanabe , Riichiro Takemura , Tomonori Sekiguchi
CPC分类号： G11C7/1039 , G11C7/1075 , G11C16/26
摘要： The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.
摘要翻译： 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级中将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以对一系列用于读取存储在非易失性半导体存储器中的数据的处理进行流水线控制，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。
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公开(公告)号：US20090116363A1
公开(公告)日：2009-05-07
申请号：US12261032
申请日：2008-10-30
CPC分类号： G11B7/0025 , G11B7/24006
摘要： In an information memory apparatus having minute areas for storing information arranged in x, y and z directions three-dimensionally, parallel rays are irradiated to a memory area MA in a direction perpendicular to a z-axis to take projection images of the memory area MA while rotating the memory area MA around the z-axis little by little. The light rays irradiated at this time have a size which covers at least a direction of an x-y plane of the memory area. A computation unit PU finds data and addresses of minute areas distributed three-dimensionally by performing computation based upon the principle of computer tomography on the projection images. As for data writing, a change is given to optical transmissivity or light emission characteristics by irradiating laser light focused by a lens OL placed outside the memory area to a desired minute area and causing heat denaturation within the pertinent minute area.
摘要翻译： 在具有用于以三维方式存储以x，y和z方向排列的信息的微小区域的信息存储装置中，在垂直于z轴的方向上将平行光线照射到存储区域MA，以拍摄存储区域MA的投影图像 同时围绕z轴逐渐旋转存储区域MA。 此时照射的光线具有至少覆盖存储区域的x-y平面的方向的尺寸。 计算单元PU通过基于投影图像上的计算机断层摄影的原理执行计算，找到三维分布的微小区域的数据和地址。 对于数据写入，通过将放置在存储区域外部的透镜OL聚焦的激光照射到期望的微小区域并且在相关的微小区域内引起热变性，来对光学透射率或发光特性进行改变。
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公开(公告)号：US20090116309A1
公开(公告)日：2009-05-07
申请号：US12348306
申请日：2009-01-04
IPC分类号： G11C7/00
CPC分类号： G11C7/1027 , G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C29/028 , G11C2207/002
摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.
摘要翻译： 提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。 在每个子放大器SAMP中提供可以根据读使能信号RD1，RD2设置两种电流之一的电流控制电路IC。 在定时控制器的控制下，在脉冲串读取操作中的周期数对应的定时产生读使能信号RD1，RD2。 电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD1被设置为较大，而当前控制电路IC中的电流在下一个和随后的脉冲串中被RD2设置得较小 读周期。 因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。
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公开(公告)号：US20090102524A1
公开(公告)日：2009-04-23
申请号：US12208978
申请日：2008-09-11
申请人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
发明人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C19/00
摘要： Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal.
摘要翻译： 公开了一种定时控制电路，其接收具有周期T1的第一时钟，以相等间隔彼此间隔开的L个不同相位的一组第二时钟，以及提供给其的选择信号m，n，并产生从 第一时钟信号的上升沿大约为td = m.T1 + n。（T2 / L）的延迟td。 定时控制电路包括粗延迟电路和精细延迟电路。 粗延迟电路包括用于在激活信号被激活之后对第一时钟信号的上升沿进行计数的计数器，并产生其第一时钟信号的延迟量近似为m.T1的粗定时信号。 精细延迟电路包括并联设置的L个多相时钟控制延迟电路，延迟n.T2 / L，通过L相第二时钟组的相应时钟对粗略定时信号进行采样的定时， 或者产生延迟脉冲，从而产生精细定时信号。
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