公开(公告)号：US20160334208A1

公开(公告)日：2016-11-17

申请号：US14737475

申请日：2015-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Yi-Jing Wang

IPC: G01B11/26

CPC classification number: G03F7/70633

Abstract: The present invention provides an overlay mark information, including at least a pair of first overlay mark patterns disposed in a first layer, each first overlay mark pattern consisting of a plurality of first mark units arranged along a first direction, where each first mark unit includes at least one first pattern and at least one second pattern, and the dimension of the first pattern is different from the dimension of the second pattern. The overlay mark information also includes at least a pair of second overlay patterns disposed in the first layer, each second overlay mark pattern consisting of a plurality of second mark units arranged along the first direction, where the pattern of each first mark unit is the same as the pattern of each second mark unit after 180 degrees rotated.

Abstract translation: 本发明提供一种重叠标记信息，其包括设置在第一层中的至少一对第一覆盖标记图案，每个第一覆盖标记图案由沿着第一方向布置的多个第一标记单元组成，其中每个第一标记单元包括 至少一个第一图案和至少一个第二图案，并且所述第一图案的尺寸不同于所述第二图案的尺寸。 覆盖标记信息还包括设置在第一层中的至少一对第二覆盖图案，每个第二覆盖标记图案由沿着第一方向布置的多个第二标记单元组成，其中每个第一标记单元的图案是相同的 作为180度旋转后的每个第二标记单元的图案。

公开(公告)号：US09496182B2

公开(公告)日：2016-11-15

申请号：US14539175

申请日：2014-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/76 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L21/823821 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device comprises a substrate, a semiconductor fin, a first isolation structure and a first dummy structure. The semiconductor fin comprises a first sub-fin and a second sub-fin protruding from a surface of the substrate. The first isolation structure is disposed in the semiconductor fin used for electrically isolating the first sub-fin and the second sub-fin. The first dummy structure is disposed on the first isolation structure and laterally extends beyond the first isolation structure along a long axis of the semiconductor fin, so as to partially overlap a portion of the first sub-fin and a portion of the second sub-fin.

Abstract translation: 半导体器件包括衬底，半导体鳍片，第一隔离结构和第一虚拟结构。 半导体鳍片包括从衬底的表面突出的第一子鳍片和第二子鳍片。 第一隔离结构设置在用于电隔离第一子鳍片和第二子鳍片的半导体鳍片中。 第一虚拟结构设置在第一隔离结构上，并且沿着半导体翅片的长轴横向延伸超过第一隔离结构，从而部分地与第一子鳍的一部分和第二子鳍的一部分重叠 。

公开(公告)号：US09496176B1

公开(公告)日：2016-11-15

申请号：US15176142

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor structure, a plurality of gate structures, at least one source/drain structure, at least one trench, a dielectric pattern, and a conductive structure. The gate structures are disposed on the semiconductor structure. The source/drain structure is disposed between two adjacent gate structures. The trench is disposed between the two adjacent gate structures and corresponding to the source/drain structure. The dielectric pattern is disposed on sidewalls of the trench. The conductive structure is disposed in the trench and electrically connected to the source/drain structure. The conductive structure includes a first portion surrounded by the dielectric pattern and a second portion connected to the source/drain structure, and the first portion is disposed on the second portion. A width of the first portion is smaller than a width of the second portion.

Abstract translation: 半导体器件包括半导体结构，多个栅极结构，至少一个源极/漏极结构，至少一个沟槽，电介质图案和导电结构。 栅极结构设置在半导体结构上。 源极/漏极结构设置在两个相邻栅极结构之间。 沟槽设置在两个相邻栅极结构之间并对应于源极/漏极结构。 电介质图案设置在沟槽的侧壁上。 导电结构设置在沟槽中并电连接到源极/漏极结构。 导电结构包括被电介质图案包围的第一部分和连接到源极/漏极结构的第二部分，第一部分设置在第二部分上。 第一部分的宽度小于第二部分的宽度。

公开(公告)号：US20160315008A1

公开(公告)日：2016-10-27

申请号：US15176142

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor structure, a plurality of gate structures, at least one source/drain structure, at least one trench, a dielectric pattern, and a conductive structure. The gate structures are disposed on the semiconductor structure. The source/drain structure is disposed between two adjacent gate structures. The trench is disposed between the two adjacent gate structures and corresponding to the source/drain structure. The dielectric pattern is disposed on sidewalls of the trench. The conductive structure is disposed in the trench and electrically connected to the source/drain structure. The conductive structure includes a first portion surrounded by the dielectric pattern and a second portion connected to the source/drain structure, and the first portion is disposed on the second portion. A width of the first portion is smaller than a width of the second portion.

Abstract translation: 半导体器件包括半导体结构，多个栅极结构，至少一个源极/漏极结构，至少一个沟槽，电介质图案和导电结构。 栅极结构设置在半导体结构上。 源极/漏极结构设置在两个相邻栅极结构之间。 沟槽设置在两个相邻栅极结构之间并对应于源极/漏极结构。 电介质图案设置在沟槽的侧壁上。 导电结构设置在沟槽中并电连接到源极/漏极结构。 导电结构包括被电介质图案包围的第一部分和连接到源极/漏极结构的第二部分，第一部分设置在第二部分上。 第一部分的宽度小于第二部分的宽度。

公开(公告)号：US20160293725A1

公开(公告)日：2016-10-06

申请号：US14704994

申请日：2015-05-06

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate is provided. At least a transistor including a dummy gate is formed on the substrate and the transistor is embedded in an interlayer dielectric (ILD) layer. A first removal process is performed to remove a portion of the dummy gate to form a first recess in the transistor. An etching process is subsequently performed to remove a portion of the ILD layer to widen the first recess and to form a widened first recess. A second removal process is subsequently performed to remove the dummy gate entirely and to form a second recess in the transistor. A metal gate is formed in the second recess and followed by forming an insulating cap layer on the metal gate.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括以下步骤。 提供基板。 在衬底上形成至少包括伪栅极的晶体管，并且将晶体管嵌入在层间电介质层（ILD）层中。 执行第一去除处理以去除伪栅极的一部分以在晶体管中形成第一凹部。 随后进行蚀刻处理以去除ILD层的一部分以加宽第一凹部并形成加宽的第一凹部。 随后执行第二去除处理以完全去除伪栅极并在晶体管中形成第二凹槽。 在第二凹部中形成金属栅极，然后在金属栅极上形成绝缘盖层。

公开(公告)号：US20160284641A1

公开(公告)日：2016-09-29

申请号：US14692762

申请日：2015-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Yu-Cheng Tung

IPC: H01L23/522 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/3085 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/00 ,  H01L29/66545 ,  H01L29/66553

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the first hard mask comprises silicon nitride.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：其上具有栅极结构的衬底和围绕栅极结构的第一层间电介质（ILD）层; 栅极结构上的第一个硬掩模; 以及栅极结构上的第二硬掩模，其中所述第一硬掩模与所述第二硬掩模的两侧相邻，并且所述第一硬掩模和所述第一硬掩模包括氮化硅。

公开(公告)号：US20160268142A1

公开(公告)日：2016-09-15

申请号：US14683120

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/311 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/3086

Abstract: A manufacturing method of a patterned structure of a semiconductor device includes following steps. A plurality of support features are formed on a substrate. A first conformal spacer layer is formed on the support features and a surface of the substrate, a second conformal spacer layer is formed on the first conformal spacer layer, and a covering layer is formed on the second conformal spacer layer. A gap between the support features is filled with the first conformal spacer layer, the second conformal spacer layer, and the covering layer. A first process is performed to remove a part of the covering layer, the second conformal spacer layer, and the first conformal spacer layer. A second process is performed to remove the support features or the first conformal spacer layer between the support feature and the second conformal spacer layer to expose a part of the surface of the substrate.

Abstract translation: 半导体器件的图案化结构的制造方法包括以下步骤。 在基板上形成多个支撑特征。 第一共形间隔层形成在支撑特征和基板的表面上，在第一共形间隔层上形成第二共形间隔层，并且在第二共形间隔层上形成覆盖层。 支撑特征之间的间隙填充有第一共形间隔层，第二共形间隔层和覆盖层。 执行第一处理以去除覆盖层，第二共形间隔层和第一共形间隔层的一部分。 执行第二过程以移除支撑特征和第二共形间隔层之间的支撑特征或第一共形间隔层，以暴露基底表面的一部分。

公开(公告)号：US09397008B1

公开(公告)日：2016-07-19

申请号：US14691586

申请日：2015-04-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/027

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A manufacturing method of a conductive structure in a semiconductor device includes the following steps. A plurality of gate structures are formed on a semiconductor structure, and a first dielectric layer is formed in space between the gate structures. A first process is then performed to remove at least a part of the first dielectric layer in the space between the gate structures. A second dielectric layer is then formed and covers the gate structures so as to form at least one air void in the space between the gate structures. A second process is performed to form at least one opening penetrating the second dielectric layer and exposing the air void. The air void exposed by the opening is then filled with at least one conductive material for forming a conductive structure between the gate structures.

Abstract translation: 半导体器件中的导电结构的制造方法包括以下步骤。 在半导体结构上形成多个栅极结构，并且在栅极结构之间的空间中形成第一介电层。 然后执行第一处理以去除栅极结构之间的空间中的第一介电层的至少一部分。 然后形成第二电介质层并覆盖栅极结构，以便在栅极结构之间的空间中形成至少一个空气空隙。 执行第二过程以形成穿透第二电介质层并暴露空气空隙的至少一个开口。 然后用至少一个导电材料填充由开口暴露的空气孔，用于在栅极结构之间形成导电结构。

公开(公告)号：US09385236B1

公开(公告)日：2016-07-05

申请号：US14748240

申请日：2015-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ying Sun ,  En-Chiuan Liou ,  Ming-Shing Chen ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  G06F17/50

CPC classification number: H01L29/7853 ,  G06F17/5081 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/7856

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plurality of fin shaped structures and a dummy gate structure. The fin shaped structures are disposed in a substrate, where at least one of the fin shaped structures has a tipped end. The dummy gate structure is disposed on the substrate, and includes an extending portion covering the tipped end.

Abstract translation: 半导体器件及其形成方法，半导体器件包括多个鳍状结构和虚拟栅极结构。 翅片状结构设置在基板中，其中至少一个翅片形结构具有尖端。 虚拟栅极结构设置在基板上，并且包括覆盖端部的延伸部分。

公开(公告)号：US20160133510A1

公开(公告)日：2016-05-12

申请号：US14534180

申请日：2014-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  G03F7/70466 ,  G03F7/70633 ,  G03F9/7046

Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern and a first alignment mark and a second reticle is used to form a second pattern and a second alignment mark in a same layer. A third reticle is aligned to the first alignment mark and the second alignment mark, to obtain an overlay correction value; additionally, a third reticle is aligned to the first alignment mark to obtain a first overlay correction value, a third reticle is aligned to the second alignment mark to obtain a second overlay correction value, and a total overlay correction value is obtained by trading off the first overlay correction value and the second overlay correction value. The third reticle is used to form a third pattern by aligning the third reticle with the total overlay correction value.

Abstract translation: 一种制造集成电路的方法包括以下步骤。 第一掩模版用于形成第一图案，第一对准标记和第二标线用于在同一层中形成第二图案和第二对准标记。 第三掩模版与第一对准标记和第二对准标记对准，以获得覆盖校正值; 此外，第三掩模版与第一对准标记对准以获得第一覆盖校正值，第三掩模版与第二对准标记对准以获得第二覆盖校正值，并且总重叠校正值通过将第 第一重叠校正值和第二覆盖校正值。 第三掩模版用于通过将第三掩模版与总覆盖校正值对准来形成第三图案。