公开(公告)号：US20170194314A1

公开(公告)日：2017-07-06

申请号：US15007163

申请日：2016-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wei Lee ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/7436 ,  H01L29/861

Abstract: An ESD protection semiconductor device includes a substrate, a buried layer buried in the substrate, a first well formed in the substrate, a first doped region formed in the first well, a second doped region formed in the first well and adjacent to the first doped region, a second well formed in the first well, and a third doped region formed in the second well. The buried layer, the first well, the first doped region, and the third doped region include a first conductivity type while the second doped region and the second well include a second conductivity type complementary to the first conductivity type. The second well is spaced apart from the first doped region and the second doped region by the first well.

公开(公告)号：US09640527B2

公开(公告)日：2017-05-02

申请号：US14728053

申请日：2015-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ting Lin ,  Yi-Chun Chen ,  Tien-Hao Tang

IPC: H01L21/8234 ,  H01L23/58 ,  H01L27/02

CPC classification number: H01L27/0274 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/861

Abstract: An electrostatic discharge (ESD) protection device includes a first trigger element and a first silicon control rectifier (SCR) element. The first trigger element has a first parasitic bipolar junction transistor (BJT) formed in a substrate. The first SCR element has a second parasitic BJT formed in the substrate. The first parasitic BJT and the second parasitic BJT has a common parasitic bipolar base, and the first parasitic BJT has a trigger voltage substantially lower than that of the second parasitic BJT.

公开(公告)号：US09607977B1

公开(公告)日：2017-03-28

申请号：US14920902

申请日：2015-10-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8249 ,  H01L21/8234

CPC classification number: H01L21/823475 ,  H01L21/8249 ,  H01L27/027 ,  H01L29/1095 ,  H01L29/78 ,  H01L29/7816

Abstract: An electrostatic discharge protection device includes an anode, a cathode, a negative voltage holding transistor and a positive voltage holding transistor. The anode is coupled to an input terminal, and the cathode is coupled to a ground. The negative voltage holding transistor includes an N-well. The positive voltage holding transistor includes an N-well. The N-well of the positive voltage holding transistor and the N-well of the negative voltage holding transistor are coupled together and are float. The negative voltage holding transistor and the positive voltage holding transistor are coupled between the anode and the cathode in a manner of back-to-back.

公开(公告)号：US20170084604A1

公开(公告)日：2017-03-23

申请号：US14860788

申请日：2015-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Shan Tseng ,  Yu-Cheng Liao ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02

CPC classification number: H01L27/0266 ,  H01L27/0207 ,  H01L27/0255 ,  H01L27/1203 ,  H01L28/00

Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.

公开(公告)号：US09564436B2

公开(公告)日：2017-02-07

申请号：US14082529

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H02H9/04 ,  H01L27/092 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/092 ,  H01L27/0277 ,  H01L27/088

Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.

Abstract translation: 描述了一种半导体器件，包括包括第一区域和第二区域的衬底，第一区域中的第一导电类型的第一MOS元件和第二区域中的第一导电类型的第二MOS元件。 第一区域比第二区域更靠近基板的拾取区域。 衬底具有第二导电类型。 第一区域中的衬底中的第一导电通路的底部深度小于第二区域中的衬底中的第二导电通路的深度。

公开(公告)号：US09559091B2

公开(公告)日：2017-01-31

申请号：US14745458

申请日：2015-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L27/02 ,  H01L29/861 ,  H01L21/76 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.

Abstract translation: 制造鳍式二极管结构的方法包括提供衬底，在所述衬底中形成掺杂阱，在所述掺杂阱中形成至少一个第一导电类型的掺杂区或第二掺杂型的至少一个掺杂区，执行蚀刻工艺 到所述第一导电类型的掺杂区域或第二导电类型的所述掺杂区域，以在所述第一导电类型的掺杂区域上或在所述第二导电类型的所述掺杂区域上形成多个鳍片，在所述鳍片之间形成浅沟槽隔离，并执行 对所述翅片进行掺杂工艺以形成第一导电类型的鳍片和第二导电类型的鳍片。

公开(公告)号：US20160293593A1

公开(公告)日：2016-10-06

申请号：US14691126

申请日：2015-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Yi-Chun Chen ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/36 ,  H01L29/10

CPC classification number: H01L27/0266 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36

Abstract: A semiconductor structure comprises a well, a first lightly doped region, a second lightly doped region, a first heavily doped region, a second heavily doped region and a gate. The first lightly doped region is disposed in the well. The second lightly doped region is disposed in the well and separated from the first lightly doped region. The first heavily doped region is disposed in the first lightly doped region. The second heavily doped region is partially disposed in the second lightly doped region. The second heavily doped region has a surface contacting the well. The gate is disposed on the well between the first heavily doped region and the second heavily doped region. The well has a first doping type. The first lightly doped region, the second lightly doped region, the first heavily doped region and the second heavily doped region have a second doping type.

Abstract translation: 半导体结构包括阱，第一轻掺杂区，第二轻掺杂区，第一重掺杂区，第二重掺杂区和栅极。 第一轻掺杂区域设置在阱中。 第二轻掺杂区域设置在阱中并与第一轻掺杂区域分离。 第一重掺杂区域设置在第一轻掺杂区域中。 第二重掺杂区域部分地设置在第二轻掺杂区域中。 第二重掺杂区域具有接触阱的表面。 栅极设置在第一重掺杂区域和第二重掺杂区域之间的阱上。 该井具有第一种掺杂型。 第一轻掺杂区域，第二轻掺杂区域，第一重掺杂区域和第二重掺杂区域具有第二掺杂类型。

公开(公告)号：US09443841B2

公开(公告)日：2016-09-13

申请号：US14986741

申请日：2016-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Ya-Ting Lin ,  Tien-Hao Tang

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/74 ,  H01L29/08 ,  H01L29/06 ,  H01L29/87 ,  H01L29/40

CPC classification number: H01L27/0262 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/402 ,  H01L29/7432 ,  H01L29/87

Abstract: An electrostatic discharge protection structure comprises an isolation layer, a high voltage P-well, an N-well, a P-well, a first doped region of N-type conductivity, a second doped region of P-type conductivity, a third doped region of N-type conductivity, a fourth doped region of P-type conductivity, an anode, and a cathode. The isolation layer is disposed on a substrate. The high voltage P-well is disposed on the isolation layer. The N-well is disposed in the high voltage P-well. The P-well is disposed in the high voltage P-well, and the P-well is separated from the N-well. The first and the second doped regions are disposed in the N-well. The third and the fourth doped regions are disposed in the P-well. The anode is electrically connected to the first doped region and the second doped region, and the cathode is electrically connected to the fourth doped region.

Abstract translation: 静电放电保护结构包括隔离层，高电压P阱，N阱，P阱，N型导电的第一掺杂区，P型导电的第二掺杂区，第三掺杂区 N型导电性区域，P型导电性的第四掺杂区域，阳极和阴极。 隔离层设置在基板上。 高压P阱设置在隔离层上。 N阱设置在高压P阱中。 P阱设置在高电压P阱中，P阱与N阱分离。 第一和第二掺杂区域设置在N阱中。 第三和第四掺杂区域设置在P阱中。 阳极电连接到第一掺杂区域和第二掺杂区域，阴极电连接到第四掺杂区域。

公开(公告)号：US09325164B2

公开(公告)日：2016-04-26

申请号：US14492089

申请日：2014-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H02H1/00 ,  H02H3/22 ,  H02H9/02 ,  H02H3/20 ,  H02H3/02

CPC classification number: H02H9/046

Abstract: An electrostatic discharge (ESD) protection device is disclosed. The ESD protection device comprises a trigger circuit, a switch, and an output buffer. When an ESD event occurs, the trigger circuit turns on the switch. One part of the current of the electrostatic discharge (ESD) event may be routed to a ground through the switch from the output buffer coupled to the output pad.

Abstract translation: 公开了一种静电放电（ESD）保护装置。 ESD保护装置包括触发电路，开关和输出缓冲器。 当发生ESD事件时，触发电路接通开关。 静电放电（ESD）事件的一部分电流可以通过开关从连接到输出板的输出缓冲器路由到地。

公开(公告)号：US20160087423A1

公开(公告)日：2016-03-24

申请号：US14492089

申请日：2014-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H02H3/20 ,  H02H1/00 ,  H02H3/02

CPC classification number: H02H9/046

Abstract: An electrostatic discharge (ESD) protection device is disclosed. The ESD protection device comprises a trigger circuit, a switch, and an output buffer. When an ESD event occurs, the trigger circuit turns on the switch. One part of the current of the electrostatic discharge (ESD) event may be routed to a ground through the switch from the output buffer coupled to the output pad.